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DP83861 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP83861 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 88 page  © 2001 National Semiconductor Corporation www.national.com General Description The DP83861 is a full featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83861 uses state of the art 0.18 µm , 1.8 V/3.3 V CMOS technology, fabricated at National Semiconductor’s South Portland Maine facility. The DP83861 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII) or the IEEE 802.3z Gigabit Media Independent Interface (GMII). Applications The DP83861 fits applications in: s 10/100/1000 Mb/s capable node cards s Switches with 10/100/1000 Mb/s capable ports s High speed uplink ports (backbone) System Diagram ETHERNET DP83861 STATUS LEDs RJ-45 100BASE-TX MII/GMII MAC CLOCK 125 MHz or 25 MHz 1000BASE-T DP83820 10BASE-T 10/100/1000Mb/s 10/100/1000Mb/s Ethernet Physical Layer Features s 100BASE-TX and 1000BASE-T compliant s Fully compliant to IEEE 802.3u 100BASE-TX and IEEE 802.3z/ab 1000BASE-T specifications. Fully integrated and fully compliant ANSI X3.T12 PMD physical sublayer that includes adaptive equalization and Baseline Wan- der compensation s 10BASE-T compatible s IEEE 802.3u Auto-Negotiation and Parallel Detection – Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s Full Duplex and Half Duplex devices s Interoperates with first generation 1000BASE-T Physical layer transceivers s 3.3V MAC interfaces: – IEEE 802.3u MII – IEEE 802.3z GMII s LED support: Link, Speed, Activity, Collision, TX and RX s Supports 125 MHz or 25 MHz reference clock s Requires only one 1.8 V and one 3.3 V supply s Supports MDIX at 10, 100, and 1000 Mb/s s Supports JTAG (IEEE1149.1) s Dissipates 1 watt in 10/100 Mb/s mode s Programmable Interrupts s 208-pin PQFP package DP83861VQM-3 EN Gig PHYTER ® 10/100/1000 Ethernet Physical Layer PRELIMINARY April 2001 PHYTER® is a registered trademark of National Semiconductor Corporation. |
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