Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

AD9864 Datasheet(PDF) 6 Page - Analog Devices

Part # AD9864
Description  IF Digitizing Subsystem
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9864 Datasheet(HTML) 6 Page - Analog Devices

Back Button AD9864 Datasheet HTML 2Page - Analog Devices AD9864 Datasheet HTML 3Page - Analog Devices AD9864 Datasheet HTML 4Page - Analog Devices AD9864 Datasheet HTML 5Page - Analog Devices AD9864 Datasheet HTML 6Page - Analog Devices AD9864 Datasheet HTML 7Page - Analog Devices AD9864 Datasheet HTML 8Page - Analog Devices AD9864 Datasheet HTML 9Page - Analog Devices AD9864 Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 44 page
background image
AD9864
Rev. 0 | Page 6 of 44
DIGITAL SPECIFICATIONS
Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS,
fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
Temperature
Test Level
Min
Typ
Max
Unit
DECIMATOR
Decimation Factor1
Full
IV
48
960
Pass-Band Width
Full
V
50%
fCLKOUT
Pass-Band Gain Variation
Full
IV
1.2
dB
Alias Attenuation
Full
IV
88
dBm
SPI-READ OPERATION (See Figure 30)
PC Clock Frequency
Full
IV
10
MHz
PC Clock Period (tCLK)
Full
IV
100
ns
PC Clock High (tHI)
Full
IV
45
ns
PC Clock Low (tLOW)
Full
IV
45
ns
PC to PD Setup Time (tDS)
Full
IV
2
ns
PC to PD Hold Time (tDH)
Full
IV
2
ns
PE to PC Setup Time (tS)
Full
IV
5
ns
PC to PE Hold Time (tH)
Full
IV
5
ns
SPI-WRITE OPERATION2 (See Figure 29)
PC Clock Frequency
Full
IV
10
MHz
PC Clock Period (tCLK)
Full
IV
100
ns
PC Clock High (tHI)
Full
IV
45
ns
PC Clock Low (tLOW)
Full
IV
45
ns
PC to PD Setup Time (tDS)
Full
IV
2
ns
PC to PD Hold Time (tDH)
Full
IV
2
ns
PC to PD (or DOUTB) Data Valid Time (tDV)
Full
IV
3
ns
PE to PD Output Valid to Hi-Z (tEZ)
Full
IV
8
ns
SSI2 (See Figure 32)
CLKOUT Frequency
Full
IV
0.867
26
MHz
CLKOUT Period (tCLK)
Full
IV
38.4
1153
ns
CLKOUT Duty Cycle (tHI, tLOW)
Full
IV
33
50
67
ns
CLKOUT to FS Valid Time (tV)
Full
IV
–1
+1
ns
CLKOUT to DOUT Data Valid Time (tDV)
Full
IV
–1
+1
ns
CMOS LOGIC INPUTS3
Logic 1 Voltage (VIH)
Full
IV
VDDH – 0.2
V
Logic 0 Voltage (VIL)
Full
IV
0.5
V
Logic 1 Current (IIH)
Full
IV
10
µA
Logic 0 Current (IIL)
Full
IV
10
µA
Input Capacitance
Full
IV
3
pF
CMOS LOGIC OUTPUTS2, 3, 4
Logic 1 Voltage (VOH)
Full
IV
VDDH – 0.2
V
Logic 0 Voltage (VOL)
Full
IV
0.2
V
1 Programmable in steps of 48 or 60.
2 CMOS output mode with CLOAD = 10 pF and Drive Strength = 7.
3 Absolute maximum and minimum input/output levels are VDDH + 0.3 V and –0.3 V.
4 IOL = 1 mA; specification is also dependent on drive strength setting.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com