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AD9864

SSI OUTPUT DRIVE STRENGTH SETTING

24-BIT I/O DATA

16-BIT I/O DATA

w/DVGA ENABLED

16-BIT I/O DATA

Figure 35. NF vs. SSI Output Drive Strength

(VDDx = 3.0 V, FCLK = 18 MSPS, BW = 75 kHz)

Table 10 lists the typical output rise/fall times as a function of DS

for a 10 pF load. Rise/fall times for other capacitor loads can be

determined by multiplying the typical values presented by a scal-

ing factor equal to the desired capacitive load divided by 10 pF.

Table 10. Typical Rise/Fall Times (±25%) with a 10 pF

Capacitive Load for Each DS Setting

Typ (ns)

13.5

7.2

3.7

3.2

2.8

2.3

2.0

SYNCRONIZATION USING SYNCB

Many applications require the ability to synchronize one or

more AD9864s in a way that causes the output data to be pre-

cisely aligned to an external asynchronous signal. For example,

receiver applications employing diversity often require syn-

chronization of multiple AD9864s’ digital outputs. Satellite

communication applications using TDMA methods may

require synchronization between payload bursts to compensate

for reference frequency drift and Doppler effects.

SYNCB can be used for this purpose. It is an active-low signal

that clears the clock counters in both the decimation filter and

the SSI port. The counters in the clock synthesizers are not reset

because it is presumed that the CLK signals of multiple chips

would be connected. SYNCB also resets the modulator, result-

ing in a large-scale impulse that must propagate through the

AD9864’s digital filter and SSI data formatting circuitry before

recovering valid output data. As a result, data samples unaf-

fected by this SYNCB induced impulse can be recovered 12

output data samples after SYNCB goes high (independent of

the decimation factor).

Figure 36 shows the timing relationship between SYNCB and

the SSI port’s CLKOUT and FS signals. SYNCB is an asynchro-

nous active-low signal that must remain low for at least half an

input clock period, i.e., 1/(2 × fCLK). CLKOUT remains high

while FS remains low upon SYNCB going low. CLKOUT will

become active within one to two output clock periods upon

SYNCB returning high. FS will reappear several output cycles

later, depending on the digital filter’s decimation factor and the

SSIORD setting. Note that for any decimation factor and

SSIORD setting, this delay is fixed and repeatable. To verify

proper synchronization, the FS signals of the multiple AD9864

devices should be monitored.

SYNCB

CLKOUT

Figure 36. SYNCB Timing

INTERFACING TO DSPs

The AD9864 connects directly to an Analog Devices program-

mable digital signal processor (DSP). Figure 37 illustrates an

example with the Blackfin® series of ADSP-2153x processors.

The Blackfin DSP series of 16-bit products is optimized for

telecommunications applications with its dynamic power man-

agement feature, making it well suited for portable radio prod-

ucts. The code compatible family members share the funda-

mental core attributes of high performance, low power con-

sumption, and the ease-of-use advantages of a microcontroller

instruction set.

AD9864

CLKOUT

RSCLK

SCK

SEL

MOSI

DOUTBM

ISO

RFS

DOUTAD

SPI

SSI

ADSP-2153x

SERIAL

PORT

SPI-PORT

Figure 37. Example of AD9864 and ADSP-2153x Interface

As shown in Figure 37, AD9864’s synchronous serial interface

(SSI) links the receive data stream to the DSP’s serial port

(SPORT). For AD9864 setup and register programming, the

device connects directly to ADSP-2153x’s SPI port. Dedicated

select lines (SEL) allow the ADSP-2153x to program and read

back registers of multiple devices using only one SPI port. The

DSP driver code pertaining to this interface is available on the

AD9864 Web page.

Rev. 0 | Page 22 of 44

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