AD9864 datasheet(32/44 Pages) AD

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AD9864

–3

–6

NORMALIZED FREQUENCY OFFSET ((

fIN–fIF) fCLK)

–9

–18

0.03

0.04

0.05

0.02

0.01

–12

–15

Signal estimation after the first decimation stage allows the

AGC to cope with out-of-band interferers and in-band signals

that could otherwise overload the ADC. Signal estimation after

the DVGA allows the AGC to minimize the effects of the 16-bit

truncation noise.

When the estimated signal level falls within the range of the

AGC, the AGC loop adjusts the VGA (or DVGA) attenuation

setting so that the estimated signal level is equal to the pro-

grammed level specified in the AGCR field. The absolute signal

strength can be determined from the contents of the ATTN and

RSSI field that is available in the SSI data frame when properly

configured. Within this AGC tracking range, the 6-bit value in

the RSSI field remains constant while the 8-bit ATTN field var-

ies according to the VGA/DVGA setting. Note that the ATTN

value is based on the 8 MSB contained in the AGCG field of

Registers 0x03 and 0x04.

Figure 60. Normalized RSSI Error vs. Normalized IF Frequency Offset

AUTOMATIC GAIN CONTROL (AGC)

A description of the AGC control algorithm and the user

adjustable parameters follows. First, consider the case in which

the in-band target signal is bigger than all out-of-band interfer-

ers and the DVGA is disabled. With the DVGA disabled, a

control loop based only on the target signal power measured

after DEC1 is used to control the VGA gain, and the target

signal will be tracked to the programmed reference level. If the

signal is too large, the attenuation is increased with a propor-

tionality constant determined by the AGCA setting. Large

AGCA values result in large gain changes, thus rapid tracking

of changes in signal strength. If the target signal is too small

relative to the reference level, the attenuation is reduced; but

now the proportionality constant is determined by both the

AGCA and AGCD settings. The AGCD value is effectively

subtracted from AGCA, so a large AGCD results in smaller

gain changes and thus slower tracking of fading signals.

The gain of the VGA (and DVGA) is automatically adjusted

when the AGC is enabled via the AGCR field of Register 0x06.

In this mode, the gain of the VGA is continuously updated at

fCLK/60 in an attempt to ensure that the maximum analog signal

level into the ADC does not exceed the ADC clip level and that

the rms output level of the ADC is equal to a programmable

reference level. With the DVGA enabled, the AGC control loop

also attempts to minimize the effects of 16-bit truncation noise

prior to the SSI output by continuously adjusting the DVGA’s

gain to ensure maximum digital gain while not exceeding the

programmable reference level.

This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB,

and 15 dB below the ADC saturation (clip) level by writing

values from 1 to 5 to the 3-bit AGCR field. Note that the ADC

clip level is defined to be 2 dB below its full scale (i.e., –18 dBm

at the LNA input for a matched input and maximum attenua-

tion). If AGCR is 0, automatic gain control is disabled. Since

clipping of the ADC input will degrade the SNR performance,

the reference level should also take into consideration the peak-

to-rms characteristics of the target (or interferer) signals.

The 4-bit code in the AGCA field sets the raw bandwidth of the

AGC loop. With AGCA = 0, the AGC loop bandwidth is at its

minimum of 50 Hz, assuming fCLK = 18 MHz. Each increment

of AGCA increases the loop bandwidth by a factor of √2; thus

the maximum bandwidth is 9 kHz. A general expression for the

attack bandwidth is

Referring again to Figure 58, the majority of the AGC loop

operates in the discrete time domain. The sample rate of the

loop is fCLK/60; therefore, registers associated with the AGC

algorithm are updated at this rate. The number of overload and

ADC reset occurrences within the final I/Q update rate of the

AD9864, as well as the AGC value (8 MSB), can be read from

the SSI data upon proper configuration.

(

) (

)

MHz

AGCA

CLK

(8)

and the corresponding attack time is

(

)

(

)

AGCA

ATTACK

100

(9)

assuming that the loop dynamics are essentially those of a

single-pole system.

The AGC performs digital signal estimation at the output of the

first decimation stage (DEC1) as well as the DVGA output that

follows the last decimation stage (DEC3). The rms power of the

I and Q signal is estimated by the equation

[]

()

[]

( n

Abs

Xest

)

(7)

The 4-bit code in the AGCD field sets the ratio of the attack

time to the decay time in the amplitude estimation circuitry.

When AGCD is zero, this ratio is one. Incrementing AGCD

multiplies the decay time constant by 21/2, allowing a 180:1

Rev. 0 | Page 32 of 44

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