DP8390D datasheet(46/58 Pages) TI1

46 / 58 page

150 Switching Characteristics (Continued)

DMA Memory Read

TLF8582 – 82

Symbol

Parameter

Min

Max

Units

bcrl

Bus Clock to Read Strobe Low

bcrh

Bus Clock to Read Strobe High

Data Setup to Read Strobe High

Data Hold from Read Strobe High

drw

DMA Read Strobe Width Out

2 bcyc b 15

raz

Memory Read High to Address TRI-STATE

bch a 40

(Notes 1 2)

asds

Address Strobe to Data Strobe

bcl a 10

dsada

Data Strobe to Address Active

bcyc b 10

avrh

Address Valid to Read Strobe High

3 bcyc b 15

Note 1

During a burst A8–A15 are not TRI-STATE if byte wide transfers are selected On the last transfer A8–A15 are TRI-STATE as shown above

Note 2

These limits include the RC delay inherent in our test method These signals typically turn off within bch a 15 ns enabling other devices to drive these

lines with no contention

DP8390D Datasheet(PDF) 46 Page - Texas Instruments

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