WM8962B datasheet(132/295 Pages) WOLFSON

132 / 295 page

WM8962

132

Rev 4.3

The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the

output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to optimise

the power consumption according to the operating conditions. This can take two forms, which are

selected using the CP_DYN_PWR register bit.



Dynamic control (CP_DYN_PWR = 1)

Under Register control, the HPOUTL_VOL and HPOUTR_VOL register settings are used to control

the charge pump mode of operation.

Under Dynamic control, the audio signal level in the DAC is also used to control the charge pump

mode of operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be

optimised in real time.

When selecting Register control

(CP_DYN_PWR = 0), a ‘1’ must be written to the HPOUT_VU bit to

complete the mode change. HPOUT_VU is defined in the “Headphone Output Paths” section (Table

80).

Note that, when selecting Dynamic control (CP_DYN_PWR = 1), the Charge Pump mode change is

implemented immediately when CP_DYN_PWR is updated.

When digital sidetone is used (see “Digital Mixing”), it is recommended that the Charge Pump

operates in Register Control mode only (CP_DYN_PWR = 0). This is because the Dynamic Control

mode (Class W) does not measure the sidetone signal level and hence the Charge Pump

configuration cannot be optimised for all signal conditions when digital sidetone is enabled; this could

lead to signal clipping.

When Virtual Surround Sound (VSS), HD Bass or DAC ReTune

is used (see “DAC Signal Path

Enhancements

”), it is recommended that the Charge Pump operates in Register Control mode only

(CP_DYN_PWR = 0). This is because the Dynamic Control mode (Class W) does not measure the

DSP Signal Enhancements level and hence the Charge Pump cannot be optimised for all signal

conditions when VSS, HD Bass or DAC ReTune is enabled; this could lead to signal clipping.

Under the recommended usage conditions of the WM8962, the Charge Pump will be enabled by

running the default headphone Start-

Up sequence as described in the “Control Write Sequencer”

section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user

does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register

control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.

The SYSCLK signal must be present for the charge pump to function. The clock division from MCLK

(or the internal oscillator) is handled transparently by the WM8962 without user intervention, as long

as SYSCLK and sample rates are set correctly (see “Clocking and Sample Rates” section). The clock

divider ratio depends on the SAMPLE_RATE[2:0] and MCLK_RATE[3:0] register settings.

The Charge Pump control fields are described in Table 81.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R72 (48h)

Charge Pump

CP_ENA

Enable charge-pump digits

0 = disable

1 = enable

R82 (52h)

Charge Pump

CP_DYN_PWR

Enable dynamic charge pump

power control

0 = Charge pump controlled by

volume register settings (Class G)

1 = Charge pump controlled by real-

time audio level (Class W)

Class W is recommended for lowest

power consumption

When selecting CP_DYN_PWR=0,

a ‘1’ must be written to the

HPOUT_VU bit (Register R2 or R3)

to complete the mode change.

Table 81 Charge Pump Control

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