VT82C596 datasheet(56/96 Pages) ETC

56 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-50-

Function 1 Registers - Enhanced IDE Controller

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 44 - Miscellaneous Control 1.................................RW

Reserved

........................................ always reads 0

Master Read Cycle IRDY# Wait States

0 wait states

1 wait state..............................................default

Master Write Cycle IRDY# Wait States

0 wait states

1 wait state..............................................default

Reserved (Do Not Program)...........R/W, default = 0

Bus Master IDE Status Register Read Retry

Retry bus master IDE status register read when

master write operation for DMA read is not complete

Disabled

Enabled...................................................default

2-1

Reserved (Do Not Program)...........R/W, default = 0

UltraDMA Host Must Wait for First Strobe

Before Termination

Enabled...................................................default

Disabled

Offset 45 - Miscellaneous Control 2.................................RW

Reserved

........................................ always reads 0

Interrupt Steering Swap

Don’t swap channel interrupts ................default

Swap interrupts between the two channels

5-4

Reserved

........................................ always reads 0

Memory Read Multiple Command

Disable ...................................................default

1Enable

Memory Read and Invalidate Command

Disable ...................................................default

1Enable

Secondary Channel Threshold Enable

Disable (data transfer starts immediately if

FIFO is not empty)

Enable (data transfer will not start until the

FIFO is filled to the threshold set in bits 1-0 of

Rx43) .....................................................default

Primary Channel Threshold Enable

Disable (data transfer starts immediately if

FIFO is not empty)

Enable (data transfer will not start until the

FIFO is filled to the threshold set in bits 3-2 of

Rx43) .....................................................default

Offset 46 - Miscellaneous Control 3 ................................ RW

Primary Channel Read DMA FIFO Flush

1 = Enable FIFO flush for read DMA when interrupt

asserts primary channel. ............... default=1 (enabled)

Secondary Channel Read DMA FIFO Flush

1 = Enable FIFO flush for Read DMA when interrupt

asserts secondary channel. ........... Default=1 (enabled)

Primary Channel End-of-Sector FIFO Flush

1 = Enable FIFO flush at the end of each sector for

the primary channel. ................... Default=0 (disabled)

Secondary Channel End-of-Sector FIFO Flush

1 = Enable FIFO flush at the end of each sector for

the secondary channel................. Default=0 (disabled)

3-2

Reserved

........................................ always reads 0

1-0

Max DRDY Pulse Width

Maximum DRDY# pulse width after the cycle count.

Command will deassert in spite of DRDY# status to

avoid system ready hang.

00 No limitation.......................................... default

01 64 PCI clocks

10 128 PCI clocks

11 192 PCI clocks

VT82C596 Datasheet(PDF) 56 Page - List of Unclassifed Manufacturers

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