VT82C596 datasheet(14/96 Pages) ETC

14 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-8-

Pinouts

7HFKQRORJLHV ,QF

:H &RQQHFW

CPU Interface

Signal Name

Pin #

I/O

Signal Description

CPURST

M19

CPU Reset. The VT82C596B asserts CPURST to reset the CPU during power-up.

INTR

L19

CPU Interrupt. INTR is driven by the VT82C596B to signal the CPU that an

interrupt request is pending and needs service.

NMI

L20

Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the

CPU.

The VT82C596B generates an NMI when either SERR# or IOCHK# is

asserted.

INIT

L18

Initialization. The VT82C596B asserts INIT if it detects a shut-down special cycle

on the PCI bus or if a soft reset is initiated by the register

STPCLK#

J18

Stop Clock. STPCLK# is asserted by the VT82C596B to the CPU in response to

different Power-Management events.

SMI#

P20

System Management Interrupt. SMI# is asserted by the VT82C596B to the CPU

in response to different Power-Management events.

FERR#

K19

Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on

the CPU. Internally generates interrupt 13 if active.

IGNNE#

L17

Ignore Numeric Error. This pin is connected to the “ignore error” pin on the CPU.

SLP#

K20

Sleep. Used to put the CPU to sleep. Used with slot-1 CPUs only. Not currently

used with socket-7 CPUs.

Universal Serial Bus Interface

Signal Name

Pin #

I/O

Signal Description

USBP0+

USB Port 0 Data +

USBP0-

USB Port 0 Data -

USBOC0#

USB Port 0 Over Current Detect. Port 0 is disabled if this input is low.

USBP1+

USB Port 1 Data +

USBP1-

USB Port 1 Data -

USBOC1#

USB Port 1 Over Current Detect. Port 1 is disabled if this input is low.

USBCLK

USB Clock. 48MHz clock input for Universal Serial Bus interface

System Management Bus (SMB) Interface (I

2C Bus)

Signal Name

Pin #

I/O

Signal Description

SMBCLK

R19

SMB / I

2C Clock.

SMBDATA

T20

SMB / I

2C Data.

SMBALRT# / GPI11

N17

MultiFunction Pin

SMB Alert. (Rx74[5] = 0) When the chip is enabled to allow it, assertion generates

an IRQ or SMI interrupt or a power management resume event.

General Purpose Input 11. (Rx74[5] = 1) General purpose input.

VT82C596 Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers

VT82C596 Datasheet(HTML) 14 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL