VT82C596 datasheet(59/96 Pages) ETC

59 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-53-

Function 1 Registers - Enhanced IDE Controller

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 70 – Primary IDE Status .......................................RW

Interrupt Status

Prefetch Buffer Status

Post Write Buffer Status

DMA Read Prefetch Status

DMA Write Prefetch Status

S/G Operation Complete

1-0

Reserved

........................................ always reads 0

Offset 71 – Primary Interrupt Control............................RW

7-1

Reserved

........................................ always reads 0

Flush FIFO Before Generating IDE Interrupt

Desable...................................................default

1Enable

Offset 74 – Primary IDE Command 1 .............................RW

Reload Sector Size After Last Command Register

Write

6-0

Reserved

........................................ always reads 0

Offset 75 – Primary IDE Command 2 .............................RW

Set Controller to Perform PIO Mode Data Port

Prefetch

Set Controller to Perform PIO Mode Data Port

Buffer Write

Set Controller to Perform DMA Mode Read

Pipeline Operation

Set Controller to Perform DMA Mode Write

Pipeline Operation

Stop S/G Bus Master

2-0

Reserved

........................................ always reads 0

Offset 78 – Secondary IDE Status ................................... RW

Interrupt Status

Prefetch Buffer Status

Post Write Buffer Status

DMA Read Prefetch Status

DMA Write Prefetch Status

S/G Operation Complete

1-0

Reserved

........................................ always reads 0

Offset 79 - Secondary Interrupt Control ........................ RW

7-1

Reserved

........................................ always reads 0

Flush FIFO Before Generating IDE Interrupt

Desable .................................................. default

1Enable

Offset 7C – Secondary IDE Command 1 ........................ RW

Reload Sector Size After Last Command Register

Write

6-0

Reserved

........................................ always reads 0

Offset 7D – Secondary IDE Command 2 ........................ RW

Set Controller to Perform PIO Mode Data Port

Prefetch

Set Controller to Perform PIO Mode Data Port

Buffer Write

Set Controller to Perform DMA Mode Read

Pipeline Operation

Set Controller to Perform DMA Mode Write

Pipeline Operation

Stop S/G Bus Master

2-0

Reserved

........................................ always reads 0

VT82C596 Datasheet(PDF) 59 Page - List of Unclassifed Manufacturers

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