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VT82C596 Datasheet(PDF) 70 Page - List of Unclassifed Manufacturers |
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VT82C596 Datasheet(HTML) 70 Page - List of Unclassifed Manufacturers |
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70 / 96 page ![]() VT82C596B Revision 0.3 June 17, 1999 -64- Function 3 Registers - Power Management and SMBus 7HFKQRORJLHV ,QF :H &RQQHFW :H &RQQHFW Offset 5B-58 – GP2/3 Timer Control (0000 0000h) ........RW 31-24 Reserved ........................................ always reads 0 23-16 GP3 Timer Count Value (base defined by bits 5-4) Write to load count value; Read to get current count 15-8 GP2 Timer Count Value (base defined by bits 1-0) Write to load count value; Read to get current count 7 GP3 Timer Start On setting this bit to 1, the GP3 timer loads the value defined by bits 23-16 of this register and starts counting down. The GP3 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP3 timer counts down to zero, then the GP3 Timer Timeout Status bit is set to one (bit-13 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP3 Timer Timeout Enable bit is set (bit-13 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. 6 GP3 Timer Automatic Reload This bit is set to one to enable the GP3 timer to reload automatically after counting down to 0. 5-4 GP3 Timer Base 00 Disable ...................................................default 01 1/4 msec 10 1 second 11 1 minute 3 GP2 Timer Start On setting this bit to 1, the GP2 timer loads the value defined by bits 15-8 of this register and starts counting down. The GP2 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP2 timer counts down to zero, then the GP2 Timer Timeout Status bit is set to one (bit-12 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP2 Timer Timeout Enable bit is set (bit-12 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. 2 GP2 Timer Automatic Reload This bit is set to one to enable the GP2 timer to reload automatically after counting down to 0. 1-0 GP2 Timer Base 00 Disable ...................................................default 01 1/16 second 10 1 second 11 1 minute Offset 61 - Programming Interface Read Value ............ WO 7-0 Rx09 Read Value The value returned by the register at offset 9h (Programming Interface) may be changed by writing the desired value to this location. Offset 62 - Sub Class Read Value .................................... WO 7-0 Rx0A Read Value The value returned by the register at offset 0Ah (Sub Class Code) may be changed by writing the desired value to this location. Offset 63 - Base Class Read Value................................... WO 7-0 Rx0B Read Value The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location. |
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