DP8422V datasheet(26/60 Pages) NSC

26 / 60 page

50 Refresh Options (Continued)

523 Error Scrubbing during Refresh

The DP8420V21V22V DP84T22 support error scrubbing

during all RAS DRAM refreshes Error scrubbing during re-

fresh is selected through bits C4 – C6 with bit R9 negated

during programming Error scrubbing can not be used with

staggered refresh (see Section 80) Error scrubbing during

refresh allows a CAS or group of CASs to assert during the

all RAS refresh as shown in

Figure 18 This allows data to

be read from the DRAM array and passed through an Error

Detection And Correction Chip EDAC If the EDAC deter-

mines that the data contains a single bit error and corrects

that error the refresh cycle can be extended with the input

extend refresh EXTNDRF and a read-modify-write opera-

tion can be performed by asserting WE It is the responsibili-

ty of the designer to ensure that WE is negated The

DP8422V DP84T22 have a 24-bit internal refresh address

counter that contains the 11 row 11 column and 2 bank

addresses The DP8420V21V have a 22-bit internal refresh

address counter that contains the 10 row 10 column and 2

bank addresses These counters are configured as bank

column row with the row address as the least significant

bits The bank counter bits are then used with the program-

ming selection to determine which CAS or group of CASs

will assert during a refresh

TLF11109 – 30

FIGURE 18 Error Scrubbing during Refresh

DP8422V Datasheet(PDF) 26 Page - National Semiconductor (TI)