DP8422V datasheet(17/60 Pages) NSC

17 / 60 page

40 Port A Access Modes (Continued)

45 ADDITIONAL ACCESS SUPPORT FEATURES

To support the different modes of accessing the DP8420V

21V22V DP84T22 offer other access features These ad-

ditional features include Address Latches and Column In-

crement (for pageburst mode support) Address Pipelining

and Delay CAS (to allow the user with a multiplexed bus to

ensure valid data is present before CAS is asserted)

451 Address Latches and Column Increment

The Address Latches can be programmed through pro-

gramming bit B0 They can be programmed to either latch

the address or remain in a fall-through mode If the address

latches are used to latch the address the controller will

function as follows

In Mode 0 the rising edge of ALE places the latches in fall-

through once ALE is negated the address present in the

row column and bank input is latched

In Mode 1 the address latches are in fall through mode until

ADS is asserted ADS asserted latches the address

Once the address is latched the column address can be

incremented with the input COLINC COLINC can be used

for sequential accesses of static column DRAMs COLINC

can also be used with the ECAS inputs to support sequen-

tial accesses to page mode DRAMs as shown in

Figure 10

COLINC should only be asserted when the signal RFIP is

negated during an access since this input functions as ex-

tended refresh when RFIP is asserted COLINC must be

negated (0) when the address is being latched (ADS falling

edge in Mode 1) If COLINC is asserted with all of the bits of

the column address asserted (ones) the column address

will return to zero

TLF11109 – 14

FIGURE 10 Column Increment

The address latches function differently with the DP8422V

DP84T22 The DP8422V DP84T22 will latch the address of

the currently granted port If Port A is currently granted the

address will be latched as described in Section 451 If Port

A is not granted and requests an access the address will

be latched on the first or second positive edge of CLK after

GRANTB has been negated depending on the programming

bits R0 R1

For Port B if GRANTB is asserted the address will be

latched with AREQB asserted If GRANTB is negated the

address will latch on the first or second positive edge of

CLK after GRANTB is asserted depending on the program-

ming bits R0 R1

DP8422V Datasheet(PDF) 17 Page - National Semiconductor (TI)

DP8422V Datasheet(HTML) 17 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL