DP8422V datasheet(21/60 Pages) NSC

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50 Refresh Options

The DP8420V21V22V DP84T22 support three refresh

control mode options

1 Automatic Internally Controlled Refresh

2 Externally ControlledBurst Refresh

3 Refresh RequestAcknowledge

With each of the control modes above three types of re-

fresh can be performed

1 All RAS Refresh

2 Staggered Refresh

3 Error Scrubbing During All RAS Refresh

There are three inputs EXTNDRF RFSH and DISRFSH

and two outputs RFIP and RFRQ associated with refresh

There are also ten programming bits R0 – 1 R9 C0 – 6 and

ECAS0 used to program the various types of refreshing

Asserting the input EXTNDRF extends the refresh cycle for

a single or multiple integral periods of CLK

The output RFIP is asserted one period of CLK before the

first refresh RAS is asserted If an access is currently in

progress RFIP will be asserted up to one period of CLK

before the first refresh RAS after AREQ or AREQB is nega-

ted for the access (see

Figure 13 )

The DP8420V21V22V DP84T22 will increment the re-

fresh address counter automatically independent of the re-

fresh mode used The refresh address counter will be incre-

mented once all the refresh RASs have been negated

In every combination of refresh control mode and refresh

type the DP8420V21V22V DP84T22 is programmed to

keep RAS asserted a number of CLK periods The time val-

ues of RAS low during refresh are programmed through pro-

gramming bits R0 and R1

51 REFRESH CONTROL MODES

511 Automatic Internal Refresh

The DP8420V21V22V DP84T22 have an internal refresh

clock The period of the refresh clock is generated from the

programming bits C0 – 3 Every period of the refresh clock

an internal refresh request is generated As long as a DRAM

access is not currently in progress and precharge time has

been met the internal refresh request will generate an auto-

matic internal refresh If a DRAM access is in progress the

DP8420V21V22V DP84T22 on-chip arbitration logic will

wait until the access is finished before performing the re-

fresh The refreshaccess arbitration logic can insert a re-

fresh cycle between two address pipelined accesses How-

ever the refresh arbitration logic can not interrupt an ac-

cess cycle to perform a refresh To enable automatic inter-

nally controlled refreshes the input DISRFSH must be neg-

ated

TLF11109 – 21

Explanation of Terms

RFRQ e ReFresh ReQuest internal to the DP8420V21V22V DP84T22 RFRQ has the ability to hold off a pending access

RFSH e Externally requested ReFreSH

RFIP e

ReFresh in Progress

ACIP e

Port A or Port B (DP8422V and DP84T22 only) ACcess in Progress This means that either RAS is low for an access or is in the

process of transitioning low for an access

FIGURE 13 DP8420V21V22V DP84T22 AccessRefresh Arbitration State Program

DP8422V Datasheet(PDF) 21 Page - National Semiconductor (TI)

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