DP8422V datasheet(58/60 Pages) NSC

58 / 60 page

140 Functional Differences

between the DP8420V21V22V

DP84T22 and the DP84202122

1 Extending the Column Address Strobe (CAS) after

AREQ Transitions High

The DP8420V21V22V DP84T22 allows CAS to be as-

serted for an indefinite period of time beyond AREQ (or

AREQB DP8422V DP84T22 only Scrubbing refreshes

are not affected) being negated by continuing to assert

the appropriate ECAS inputs This feature is allowed as

long as the ECAS0 input was negated during program-

ming The DP84202122 does not allow this feature

2 Dual Accessing

The DP8420V21V22V DP84T22 asserts RAS either

one or two clock periods after GRANTB has been assert-

ed or negated depending upon how the R0 bit was pro-

grammed

during

the

mode

load

operation

The

DP84202122 will always start RAS one clock period

after GRANTB is asserted or negated The above state-

ments assume that RAS precharge has been completed

by the time GRANTB is asserted or negated

3 Refresh Request Output (RFRQ)

The DP8420V21V22V DP84T22 allows RFRQ (refresh

request) to be output on the WE output pin given that

ECAS0 was negated during programming or the control-

ler was programmed to function in the address pipelining

(memory interleaving) mode The DP84202122 only al-

lows RFRQ to be output during the address pipelining

mode

4 Clearing the Refresh Request Clock Counter

The DP8420V21V22V DP84T22 allows the internal re-

fresh request clock counter to be cleared by negating

DISRFSH and asserting RFSH for at least 500 ns The

DP84202122 clears the internal refresh request clock

counter if DISRFSH remains low for at least 500 ns Once

the internal refresh request clock counter is cleared the

user is guaranteed that an internally generated RFRQ will

not be generated for at least 13 ms–15 ms (depending

upon how programming bits C0

3 were pro-

grammed)

150 DP8420V21V22V DP84T22

User Hints

1 All inputs to the DP8420V21V22V DP84T22 should be

tied high low or the output of some other device

Note One signal is active high COLINC (EXTNDRF) should be tied low

to disable

2 Each ground on the DP8420V21V22V DP84T22 must

be decoupled to the closest on-chip supply (VCC) with

01 mF ceramic capacitor This is necessary because

these grounds are kept separate inside the DP8420V

21V22V DP84T22 The decoupling capacitors should

be placed as close as possible with short leads to the

ground and supply pins of the DP8420V21V22V

DP84T22

3 The output called ‘‘CAP’’ should have a 01 mF capacitor

to ground

4 The DP8420V21V22V

DP84T22 has 20X series

damping resistors built into the output drivers of RAS

CAS address and WE RFRQ Space should be provided

for external damping resistors on the printed circuit board

(or wire-wrap board) because they may be needed The

value of these damping resistors (if needed) will vary de-

pending upon the output the capacitance of the load

and the characteristics of the trace as well as the routing

of the trace The value of the damping resistor also may

vary between the wire-wrap board and the printed circuit

board To determine the value of the series damping re-

sistor it is recommended to use an oscilloscope and look

at the furthest DRAM from the DP8420V21V22V

DP84T22 The undershoot of RAS CAS WE and the ad-

dresses should be kept to less than 05V below ground

by varying the value of the damping resistor The damp-

ing resistors should be placed as close as possible with

short leads to the driver outputs of the DP8420V21V

22V DP84T22

5 The circuit board must have a good VCC and ground

plane connection If the board is wire-wrapped the VCC

and ground pins of the DP8420V21V22V DP84T22

the DRAM associated logic and buffer circuitry must be

soldered to the VCC and ground planes

6 The traces from the DP8420V21V22V DP84T22 to the

DRAM should be as short as possible

7 ECAS0 should be held low during programming if the user

wishes that the DP8420V21V22V DP84T22 be com-

patible with a DP84202122 design

8 Parameter Changes due to Loading

All AC parameters are specified with the equivalent load

capacitances including traces of 64 DRAMs organized

as 4 banks of 18 DRAMs each Maximums are based on

worst-case conditions If an output load changes then the

AC timing parameters associated with that particular

output must be changed For example if we changed our

output load to

C e 250 pF loads on RAS0 – 3 and CAS0–3

C e 760 pF loads on Q0 – 9 and WE

we would have to modify some parameters (not all calcu-

lated here)

$308a clock to CAS asserted

(tRAH e 15 ns tASC e 0 ns)

A ratio can be used to figure out the timing change per

change in capacitance for a particular parameter by using

the specifications and capacitances from heavy and light

load timing

Ratio e

$308a wHeavy Load b $308a wLight Load

CH(CAS) b CL(CAS)

79 ns b 72 ns

125 pF b 50 pF

7ns

75 pF

$308a (actual) e (capacitance difference c

ratio) a $308a (specified)

(250 pF b 125 pF)

7ns

75 pF

79 ns

117 ns a 79 ns

907 ns

250 pF load

9 It is required that the user perform a hardware reset to

the DP8420V21V22V DP84T22 before programming

and using the chip A hardware reset consists of assert-

ing both ML and DISRFSH for a minimum of 16 positive

edges of CLK see Section 31

DP8422V Datasheet(PDF) 58 Page - National Semiconductor (TI)

DP8422V Datasheet(HTML) 58 Page - National Semiconductor (TI)

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