LM3560 datasheet(32/48 Pages) TI1

32 / 48 page

LM3560

SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013

www.ti.com

PRIVACY PWM PERIOD REGISTER (Address 0x14)

The Privacy PWM Register contains the bits to control the PWM period for the privacy indicate mode (see

Table 8).

Table 8. Privacy PWM Period Register

Bits 7-3

Bit 2

Bit 1

Bit 0

(Not Used)

(P3)

(P2)

(P1)

000 = 5.12 ms (default)

001 = 2.56 ms

010 = 1.28 ms

011 = 640 µs

1XX = 320 µs

GPIO REGISTER (Address 0x20)

The GPIO register contains the control bits which change the state of the TX1/TORCH/GPIO1 pin and the

TX2/INT/GPIO2 pins to general purpose I/O’s (GPIO’s). Additionally, bit 6 of this register contains the interrupt

configuration bit. Table 9 describes the bit description and functionality of the GPIO register. To configure the

TX1 or TX2 pins as GPIO outputs an initial double write is required to register 0x20. For example, to configure

TX2 to output a logic high, an initial write of 0xB8 would need to occur twice, to force GPIO2 low. Subsequent

writes to GPIO2 after the initial set-up, only requires a single write. To read back the GPIO inputs, a write then a

read of register 0x20 must occur each time the data is read. For example, if GPIO2 is set-up as a GPIO input

and the GPIO2 input has then changed state, first a write to 0x20 must occur, then the following read back of

must first be configured as a GPIO output (double write). For example, to configure TX2/GPIO2/INT for INT

mode a write of 0xF8 to register 0x20 must be done twice.

Table 9. GPIO Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Not

(TX2/INT/GPIO2

(TX2/INT/GPI

(TX2/INT/GPIO2

(TX1/TORCH/G

Used)

Interrupt Enable) O2 data)

O2 data

Control)

PIO1 data)

PIO1 data

PIO1 Control)

direction)

N/A

0 =

This bit is the

0 =

This bit is the

0 =

TX2/INT/GPIO2

read or write

TX2/INT/GPIO

TX2/INT/GPIO is

read or write

TX1/TORCH/GP TX1/TORCH/GP

is configured

data for the

2 is a GPIO

configured as a

data for the

IO1 is a GPIO

IO1 pin is

according to bit 3

TX2/INT/GPIO

Input (default)

TX interrupt

GPIO1 pin in

input (default)

configured as

of this register

2 pin in GPIO

(default)

GPIO mode

(default)

mode

interrupt(default

)

1 = with bits [4:3]

1 =

= 11,

TX2/INT/GPIO

TX2/INT/GPIO2

TX1/TORCHGPI TX1/TORCH/GP

TX2/INT/GPIO2

2 is a GPIO

is configured as a

O1 is an output

IO1 pin is

is an interrupt

output

GPIO

configured as a

output. See

GPIO

INTERRUPT

OUTPUT (INT

MODE).

Submit Documentation Feedback

Product Folder Links: LM3560

LM3560 Datasheet(PDF) 32 Page - Texas Instruments

LM3560 Datasheet(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL