LM3560 datasheet(33/48 Pages) TI1

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LM3560

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SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013

LED FORWARD VOLTAGE ADC (VLED MONITOR REGISTER, Address 0x30)

The VLED Monitor Register controls the internal 4 bit analog to digital converter. Bits [3:0] of this register contain

the 4-bit data of the LED voltage. This data is the digitized voltage of the highest of either VLED1 to GND or

VLED2 to GND. Bit [4] is the Manual Mode enable which provides for a manual conversion of the ADC. In

Manual Mode the Automatic Conversion is still performed. In automatic conversion mode a conversion is

performed each time a flash pulse is initiated. Bit [5] is the ADC shutdown bit. Bit [6] signals the end of

conversion. This is a read-only bit that goes high when a conversion is complete and data is ready. A read of the

VLED Monitor Register clears the End of Conversion bit (see Table 10).

Table 10. VLED Monitor Register Descriptions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Not

(End of

(ADC Shutdown)

(Manual Mode

(ADC3)

(ADC2)

(ADC1)

(ADC0)

Used)

Conversion)

Enable)

N/A

0 = Conversion in 0 = ADC is enabled

0 = Manual Mode 0000 = (VLED < 2.8V) (default)

progress(default) (default)

Disabled

0001 = (2.8V

≤ VLED < 2.9V)

(default)

0010 = (2.9V

≤ VLED < 3.0V)

0011 = (3.0V

≤ VLED < 3.1V)

1 = Conversion

1 = ADC is shutdown, 1 = Manual Mode

0100 = (3.1V

≤ VLED < 3.2V)

done

no conversion is

is Enabled

0101 = (3.2V

≤ VLED < 3.3V)

performed

0110 = (3.3V

≤ VLED < 3.4V)

0111 = (3.4V

≤ VLED < 3.5V)

1000 = (3.5V

≤ VLED < 3.6V)

1001 = (3.6V

≤ VLED < 3.7V)

1010 = (3.7V

≤ VLED < 3.8V)

1011 = (3.8V

≤ VLED < 3.9V)

1100 = (3.9V

≤ VLED < 4.0V)

1101 = (4.0V

≤ VLED < 4.1V)

1110 = (4.1V

≤ VLED < 4.2V)

1111 = (4.2V

≤ VLED)

ADC DELAY REGISTER (Address 0x31)

The ADC Delay Register programs the delay from when the EOC bit goes low to when a conversion is initiated.

This delay applies to both Manual Mode and Automatic Mode. Bit 5 is the No Delay bit and can set the delay to

effectively 0.

Table 11. ADC Delay Register Descriptions

Bit 7

Bit 6

Bit 5 (No Delay)

Bit 4 (D1)

Bit 3 (D2)

Bit 2 (D3)

Bit 1 (D4)

Bit 0

(Not

(Not used)

(D5)

Used)

0 = Delay is set by bits

Bits [4:0] programs the delay from when the EOC bit goes low to when a

[4:0](default)

conversion is started (250 µs/step).

00000 = 250 µs

1 = no delay from when the EOC

N/A

goes low to when the conversion is

01111 = 4 ms (default)

started.

11111 = 8 ms

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