TMS320DM641 datasheet(105/171 Pages) TI

105 / 171 page

External Memory Interface (EMIIF)

105

June 2003 − Revised August 2004

SPRS222C

4.8

External Memory Interface (EMIIF)

EMIF supports a glueless interface to a variety of external devices, including:

•

Pipelined synchronous-burst SRAM (SBSRAM)

•

Synchronous DRAM (SDRAM)

•

Asynchronous devices, including SRAM, ROM, and FIFOs

•

An external shared-memory device

4.8.1

EMIF Device-Specific Information

EMIF Device Speed

The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the

following requirements:

•

1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF

•

up to 1 CE space of buffers connected to EMIF

•

EMIF trace lengths between 1 and 3 inches

•

166-MHz SDRAM for 133-MHz operation

•

143-MHz SDRAM for 100-MHz operation

Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.

Verification of AC timings is mandatory when using configurations other than those specified above. TI

recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models

for Timing Analysis application report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see

the Terminal Functions table for the EMIF output signals).

For more detailed information on the DM641/DM640 EMIF peripheral, see the TMS320C6000 DSP External

Memory Interface (EMIF) Reference Guide (literature number SPRU266).

4.8.2

EMIF Peripheral Register Description(s)

Table 4−21. EMIFA Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

0180 0000

GBLCTL

EMIFA global control

0180 0004

CECTL1

EMIFA CE1 space control

0180 0008

CECTL0

EMIFA CE0 space control

0180 000C

−

Reserved

0180 0010

CECTL2

EMIFA CE2 space control

0180 0014

CECTL3

EMIFA CE3 space control

0180 0018

SDCTL

EMIFA SDRAM control

0180 001C

SDTIM

EMIFA SDRAM refresh control

0180 0020

SDEXT

EMIFA SDRAM extension

0180 0024 − 0180 003C

−

Reserved

0180 0040

PDTCTL

Peripheral device transfer (PDT) control

0180 0044

CESEC1

EMIFA CE1 space secondary control

0180 0048

CESEC0

EMIFA CE0 space secondary control

0180 004C

−

Reserved

0180 0050

CESEC2

EMIFA CE2 space secondary control

0180 0054

CESEC3

EMIFA CE3 space secondary control

0180 0058 − 0183 FFFF

–

Reserved

TMS320DM641 Datasheet(PDF) 105 Page - Texas Instruments

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