TMS320DM641 datasheet(109/171 Pages) TI

109 / 171 page

External Memory Interface (EMIIF)

109

June 2003 − Revised August 2004

SPRS222C

4.8.3.2

Programmable Synchronous Interface Timing

Table 4−24. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 4−19)

NO.

−400

−500

−600

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-EKOxH)

Setup time, read AEDx valid before AECLKOUTx high

3.1

th(EKOxH-EDV)

Hold time, read AEDx valid after AECLKOUTx high

1.5

Table 4−25. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module† (see Figure 4−19−Figure 4−21)

NO.

PARAMETER

−400

−500

−600

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

td(EKOxH-CEV)

Delay time, AECLKOUTx high to ACEx valid

1.3

6.4

1.3

4.9

td(EKOxH-BEV)

Delay time, AECLKOUTx high to ABEx valid

6.4

4.9

td(EKOxH-BEIV)

Delay time, AECLKOUTx high to ABEx invalid

1.3

td(EKOxH-EAV)

Delay time, AECLKOUTx high to AEAx valid

6.4

4.9

td(EKOxH-EAIV)

Delay time, AECLKOUTx high to AEAx invalid

1.3

td(EKOxH-ADSV)

Delay time, AECLKOUTx high to ASADS/ASRE valid

1.3

6.4

1.3

4.9

td(EKOxH-OEV)

Delay time, AECLKOUTx high to ASOE valid

1.3

6.4

1.3

4.9

td(EKOxH-EDV)

Delay time, AECLKOUTx high to AEDx valid

6.4

4.9

td(EKOxH-EDIV)

Delay time, AECLKOUTx high to AEDx invalid

1.3

td(EKOxH-WEV)

Delay time, AECLKOUTx high to ASWE valid

1.3

6.4

1.3

4.9

† The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued

(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).

− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles

(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).

− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2

TMS320DM641 Datasheet(PDF) 109 Page - Texas Instruments

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