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TMS320DM641 Datasheet(PDF) 115 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 115 Page - Texas Instruments |
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115 / 171 page  External Memory Interface (EMIIF) 115 June 2003 − Revised August 2004 SPRS222C AECLKOUTx ACEx ABE[3:0] AEA[12:3] AED[31:0] AAOE/ASDRAS/ASOE† AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† AEA13 AEA[22:14] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 11 8 9 5 5 5 4 2 11 8 9 4 4 2 1 10 3 4 WRITE APDT‡ 14 14 † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. ‡ APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 4−23. Figure 4−23. SDRAM Write Command for EMIFA |
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