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TMS320DM641 Datasheet(PDF) 131 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 131 Page - Texas Instruments |
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131 / 171 page  Inter-Integrated Circuit (I2C) 131 June 2003 − Revised August 2004 SPRS222C Table 4−37. Switching Characteristics for I2C Timings† (see Figure 4−37) NO. PARAMETER −400 −500 −600 UNIT NO. PARAMETER STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX 16 tc(SCL) Cycle time, SCL 10 2.5 µs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 µs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 21 td(SDAV-SDLH) Delay time, SDA valid to SCL high 250 100 ns 22 tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices) 0 0 0.9 µs 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb† 300 ns 25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb† 300 ns 26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb† 300 ns 27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb† 300 ns 28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs 29 Cp Capacitance for each I2C pin 10 10 pF † Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 26 24 Figure 4−37. I2C Transmit Timings |
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