TMS320DM641 datasheet(132/171 Pages) TI

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Host-Port Interface (HPI) [DM641 Only]

132

June 2003 − Revised August 2004

SPRS222C

4.11

Host-Port Interface (HPI) [DM641 Only]

The HPI is a parallel port through which a host processor can directly access the CPU memory space. The

host device functions as a master to the interface, which increases ease of access. The host and CPU can

exchange information via internal or external memory. The host also has direct access to memory-mapped

peripherals. Connectivity to the CPU memory space is provided through the enhanced DMA (EDMA)

controller. Both the host and the CPU can access the HPI control register (HPIC) and the HPI address register

(HPIA). The host can access the HPI data register (HPID) and the HPIC by using the external data and

interface control signals.

For more detailed information on the HPI peripheral, see the TMS320C6000 DSP Host Port Interface (HPI)

Reference Guide (literature number SPRU578).

4.11.1

HPI Peripheral Register Description(s) [DM641 Only]

Table 4−38. HPI Registers [DM641 Only]

HEX ADDRESS RANGE

ACRONYM

COMMENTS

−

HPID

HPI data register

Host read/write access only

0188 0000

HPIC

HPI control register

HPIC has both Host/CPU read/write access

0188 0004

HPIA

(HPIAW)†

HPI address register

(Write)

HPIA has both Host/CPU read/write access

0188 0008

HPIA

(HPIAR)†

HPI address register

(Read)

HPIA has both Host/CPU read/write access

0188 000C − 0189 FFFF

−

Reserved

018A 0000

HPI_TRCTL

HPI transfer request control

018A 0004 − 018B FFFF

−

Reserved

† Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.

4.11.2

Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only]

Table 4−39. Timing Requirements for Host-Port Interface Cycles†‡ (see Figure 4−38 through Figure 4−41)

[DM641 Only]

NO.

−400

−500

−600

UNIT

MIN

MAX

tsu(SELV-HSTBL)

Setup time, select signals§ valid before HSTROBE low

th(HSTBL-SELV)

Hold time, select signals§ valid after HSTROBE low

2.4

tw(HSTBL)

Pulse duration, HSTROBE low

4P¶

tw(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

tsu(SELV-HASL)

Setup time, select signals§ valid before HAS low

th(HASL-SELV)

Hold time, select signals§ valid after HAS low

tsu(HDV-HSTBH)

Setup time, host data valid before HSTROBE high

th(HSTBH-HDV)

Hold time, host data valid after HSTROBE high

2.8

th(HRDYL-HSTBL)

Hold time, HSTROBE low after HRDY low. HSTROBE should not be

inactivated until HRDY is active (low); otherwise, HPI writes will not complete

properly.

tsu(HASL-HSTBL)

Setup time, HAS low before HSTROBE low

th(HSTBL-HASL)

Hold time, HAS low after HSTROBE low

2.1

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

§ Select signals include: HCNTL[1:0], HR/W, and HHWIL.

¶ Select the parameter value of 4P or 12.5 ns, whichever is larger.

TMS320DM641 Datasheet(PDF) 132 Page - Texas Instruments

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