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TMS320DM641 Datasheet(PDF) 166 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 166 Page - Texas Instruments |
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166 / 171 page  General-Purpose Input/Output (GPIO) 166 June 2003 − Revised August 2004 SPRS222C 4.18.2 GPIO Peripheral Register Description(s) Table 4−79. GP0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B0 0000 GPEN GP0 enable register 01B0 0004 GPDIR GP0 direction register 01B0 0008 GPVAL GP0 value register 01B0 000C − Reserved 01B0 0010 GPDH GP0 delta high register 01B0 0014 GPHM GP0 high mask register 01B0 0018 GPDL GP0 delta low register 01B0 001C GPLM GP0 low mask register 01B0 0020 GPGC GP0 global control register 01B0 0024 GPPOL GP0 interrupt polarity register 01B0 0028 − 01B3 EFFF − Reserved 4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing Table 4−80. Timing Requirements for GPIO Inputs†‡ (see Figure 4−63) NO. −400 −500 −600 UNIT MIN MAX 1 tw(GPIH) Pulse duration, GPIx high 8P ns 2 tw(GPIL) Pulse duration, GPIx low 8P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access the GPIO register through the CFGBUS. Table 4−81. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs† (see Figure 4−63) NO. PARAMETER −400 −500 −600 UNIT MIN MAX 3 tw(GPOH) Pulse duration, GPOx high 24P − 8‡ ns 4 tw(GPOL) Pulse duration, GPOx low 24P − 8‡ ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. GPIx GPOx 4 3 2 1 Figure 4−63. GPIO Port Timing |
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