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TFP401APZP Datasheet(PDF) 17 Page - Texas Instruments

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Part # TFP401APZP
Description  TFP401x TI PanelBus Digital Receiver
PDF  32 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TFP401APZP Datasheet(HTML) 17 Page - Texas Instruments

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TFP401, TFP401A
www.ti.com
SLDS120G – MARCH 2000 – REVISED MAY 2016
Product Folder Links: TFP401 TFP401A
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TFP401 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel display
systems to receive and decode TMDS encoded RGB pixel data streams. A digital display system a host, usually
a PC or workstation, contains a DVI compliant transmitter that receives 24-bit pixel data along with appropriate
control signals and encodes them into a high-speed low voltage differential serial bit stream fit for transmission
over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a DVI
compliant receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and
control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive
circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5
meters or more, serial transmission of the pixel data is preferred. The TFP401 will support resolutions up to
UXGA.
10.2 Typical Application
Figure 18. Typical Application
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
VALUE
Power supply
3.3 V-DC @ 1 A
Input clock
Single-ended
Input clock frequency range
25 MHz – 165 MHz
Output format
24 bits/pixel
Input clock latching
Rising edge
I2C EEPROM support
No
De-skew
No



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