AVCC

AVCC – 1/2 VIDIFF

1/2 VIDIFF

a) Single-Ended Input Signal

+1/2 VIDIFF

–1/2 VIDIFF

VIDIFF

b) Differential Input Signal

_

+

Internal Termination

at 50 W

AVDD

DVI Compliant Cable

DATA

DATA

TI TFP401/401A

Receiver

DVI

Transmitter

Current

Source

14

TFP401, TFP401A

SLDS120G – MARCH 2000 – REVISED MAY 2016

www.ti.com

Product Folder Links: TFP401 TFP401A

Submit Documentation Feedback

Copyright © 2000–2016, Texas Instruments Incorporated

Figure 15. TMDS Differential Input and Transmitter Connection

Figure 16. TMDS Inputs

9.3.4 TFP401A Incorporates HSYNC Jitter Immunity

Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals

during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal

in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and

if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to

occur on the display. For this reason, a DVI-compliant receiver with HSYNC jitter immunity should be used in all

displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.

The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant

transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the

location of HSYNC. The TFP401A receiver uses the DE and clock signals to recreate stable vertical and

horizontal sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted to the nearest

eighth bit boundary, producing a stable output with respect to data, as shown in Figure 17. This ensures accurate

data synchronization at the input of the display timing controller.

This HSYNC regeneration circuit is transparent to the monitor and need not be removed even if the transmitted

HSYNC is stable. For example, the PanelBus line of DVI 1.0 compliant transmitters, such as the TFP6422 and

TFP420, do not have the HSYNC jitter problem. The TFP401A operates correctly with either compliant or

noncompliant transmitters. In contrast, the TFP401 is ideal for customers who have control over the transmit

portion of the design, such as bundled system manufacturers and for internal monitor use (the DVI connection

between monitor and panel modules).