8

TFP401, TFP401A

SLDS120G – MARCH 2000 – REVISED MAY 2016

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Copyright © 2000–2016, Texas Instruments Incorporated

AC Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(8)

Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.

Setup time, data and control signal to falling edge of ODCK

1 pixel/clock, PIXS = low, OCK_INV =

low

1.8

ns

2 pixel/clock, PIXS = high,

STAG = high, OCK_INV = low

3.8

2 pixel and STAG, PIXS = high, STAG

= low, OCK_INV = low

0.7

Hold time, data and control signal to falling edge of ODCK

1 pixel/clock, PIXS = low, OCK_INV =

low

0.6

ns

2 pixel and STAG, PIXS = high,

STAG = low, OCK_INV = low

2.5

2 pixel/clock, PIXS = high,

STAG = high, OCK_INV = low

2.9

Setup time, data and control signal to rising edge of ODCK

1 pixel/clock, PIXS = low,

OCK_INV = high

2.1

ns

2 pixel/clock, PIXS = high,

STAG = high, OCK_INV = high

4

2 pixel and STAG, PIXS = high,

STAG = low, OCK_INV = high

1.5

Hold time, data and control signal to rising edge of ODCK

1 pixel/clock, PIXS = low, OCK_INV =

high

0.5

ns

2 pixel and STAG, PIXS = high,

STAG = low, OCK_INV = high

2.4

2 pixel/clock, PIXS = high,

STAG = high, OCK_INV = high

2.1

ODCK frequency

PIX = low (1-PIX/CLK)

25

165

MHz

PIX = high (2-PIX/CLK)

12.5

82.5

ODCK duty-cycle

40%

50%

60%

Propagation delay time from PD low to Hi-Z outputs

9

ns

Propagation delay time from PDO low to Hi-Z outputs

9

ns

1e6

1600

Delay time, ODCK latching edge to QE[23:0] data output

STAG = low, PIXS = high

0.25

Minimum time PD is asserted low

9

ns

Minimum DE low

128

Tpixel