TMS320UC5409 datasheet(21/81 Pages) TI1

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TMS320UC5409

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS101E − APRIL 1999 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

HPI16 control register (HPIC)

In nonmultiplexed mode, the HPIC register is not accessible via the host. This precludes DSP-to-host or

host-to-DSP interrupts, data prefetch via the FETCH bit, and HRDY polling. Extended addressing capability still

exists (even without the XHPIA bit) because the HA bus is 16 bits wide.

HPI16 address register (HPIA)

In nonmultiplexed mode, the HPIA register is not needed because direct address inputs A[15:0] are used as

HA[15:0]. The DMA address comes directly from the HA pins. Note that the HA bus is still always latched at the

end of the host access (on the rising edge of HDS = HDS1 XNOR HDS2) in order to ensure a valid address

during the DMA write access.

host data prefetch

Since the HPIA register is not used in nonmultiplexed mode, the prefetch mechanism is not supported. Random

address accesses in nonmultiplexed mode are still faster than those in multiplexed mode because of the

separate address and data buses.

host ready logic (HRDY)

Hardware HRDY logic operation in nonmultiplexed mode is the same as that in multiplexed mode. HRDY

operation during prefetches and HRDY/FETCH bit interaction are not supported with nonmultiplexed mode.

host/DSP interrupts

Host-to-DSP and DSP-to-host interrupts are not supported by HPI16 in nonmultiplexed mode.

other HPI system considerations

operation during IDLE2

The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns

on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.

The DSP CPU does not wake up from the IDLE mode during this process.

multichannel buffered serial ports

The UC5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow

direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based

on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP provides:

D Full-duplex communication

D Double-buffer data registers, which allow a continuous data stream

D Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D Direct interface to:

−

T1/E1 framers

−

MVIP switching-compatible and ST-BUS compliant devices

−

IOM-2 compliant devices

−

AC97-compliant devices

−

Serial peripheral interface (SPI

t) devices

D Multichannel transmit and receive of up to 128 channels

D A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

D µ-law and A-law companding

D Programmable polarity for both frame synchronization and data clocks

D Programmable internal clock and frame generation

SPI is a trademark of Motorola Inc.

Not Recommended For New Designs

TMS320UC5409 Datasheet(PDF) 21 Page - Texas Instruments

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