TMS320UC5409 datasheet(64/81 Pages) TI1

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TMS320UC5409

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS101E − APRIL 1999 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0†

(see Figure 34)

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(BDRV-BCKXL)

Setup time, BDR valid before BCLKX low

− 12H

th(BCKXL-BDRV)

Hold time, BDR valid after BCLKX low

5 + 12H

tsu(BFXL-BCKXL)

Setup time, BFSX low before BCLKX low

tc(BCKX)

Cycle time, BCLKX

32H

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b,

CLKXP = 0† (see Figure 34)

PARAMETER

MASTER‡

SLAVE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low§

T − 3

T + 4

td(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high¶

C − 5

C + 3

td(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid

−2

6H +54

10H + 15

tdis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from

BCLKX low

C − 2

C + 3

tdis(BFXH-BDXHZ)

Disable time, BDX high impedance following last data bit from

BFSX high

2H+ 4

6H + 17

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

4H + 2

8H + 17

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ T = BCLKX period = (1 + CLKGDV) * 2H

C =

BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

tsu(BDRV-BCLXL)

td(BCKXH-BDXV)

th(BCKXL-BDRV)

tdis(BFXH-BDXHZ)

tdis(BCKXL-BDXHZ)

th(BCKXL-BFXL)

td(BFXL-BDXV)

td(BFXL-BCKXH)

LSB

MSB

Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

Not Recommended For New Designs

TMS320UC5409 Datasheet(PDF) 64 Page - Texas Instruments

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