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TMS320UC5409 Datasheet(PDF) 52 Page - Texas Instruments

Part # TMS320UC5409
Description  FIXED-POINT DIGITAL SIGNAL PROCESSOR
PDF  81 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320UC5409 Datasheet(HTML) 52 Page - Texas Instruments

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TMS320UC5409
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
52
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 20, Figure 21,
Figure 22, and Figure 23)
MIN
MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
5
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
tv(RDY)MSTRB
Valid time, READY after MSTRB low‡
4H−8
ns
th(RDY)MSTRB
Hold time, READY after MSTRB low‡
4H
ns
tv(RDY)IOSTRB
Valid time, READY after IOSTRB low‡
5H−8
ns
th(RDY)IOSTRB
Hold time, READY after IOSTRB low‡
5H
ns
tv(MSCL)
Valid time, MSC low after CLKOUT low
0
3
ns
tv(MSCH)
Valid time, MSC high after CLKOUT low
0
3
ns
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
MSC
MSTRB
READY
A[19:0]
CLKOUT
tv(MSCH)
tv(MSCL)
th(RDY)
th(RDY)MSTRB
tv(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
tsu(RDY)
Figure 20. Memory Read With Externally Generated Wait States
Not Recommended For New Designs



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