TMS320UC5409 datasheet(27/81 Pages) TI1

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TMS320UC5409

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS101E − APRIL 1999 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock generator (continued)

This clock generator allows system designers to select the clock source. The sources that drive the clock

generator are:

D A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of

the UC5409 to enable the internal oscillator.

D An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in

software-programmable PLL can be configured in one of two clock modes:

D PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the

CLKMD1 − CLKMD3 pins as shown in Table 8.

Table 8. Clock Mode Settings at Reset

CLKMD1

CLKMD2

CLKMD3

CLKMD

RESET VALUE

CLOCK MODE

CLKMD1

CLKMD2

CLKMD3

RESET VALUE

CLOCK MODE

E007h

PLL x 15

9007h

PLL x 10

4007h

PLL x 5

1007h

PLL x 2

F007h

PLL x 1

0000h

1/2 (PLL disabled)

F000h

1/4 (PLL disabled)

—

Reserved (Bypass mode)

Not Recommended For New Designs

TMS320UC5409 Datasheet(PDF) 27 Page - Texas Instruments

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