TMS570LS3137 datasheet(114/173 Pages) TI1

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HCLK

DMMCLK

DMMSYNC

DMMDATA

DMMnENA

D00

D01

D10

D11

D20

D21

D30

D31

D40

D41

D50

TMS570LS3137

SPNS162C – APRIL 2012 – REVISED APRIL 2015

www.ti.com

Table 6-48. Timing Requirements for DMMDATA

MIN

MAX

UNIT

tssu(DMM)

SYNC active to clk falling edge setup time

tsh(DMM)

clk falling edge to SYNC inactive hold time

tdsu(DMM)

DATA to clk falling edge setup time

tdh(DMM)

clk falling edge to DATA hold time

Figure 6-29. DMMnENA Timing

Figure 6-29 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data

width = 8, port width = 4) where none of the packets received by the DMM are sent out, leading to filling

up of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been

received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,

D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to

stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets

immediately (after 0 HCLK cycles).

114

System Information and Electrical Specifications

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