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TMS570LS3137 Datasheet(PDF) 116 Page - Texas Instruments |
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TMS570LS3137 Datasheet(HTML) 116 Page - Texas Instruments |
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116 / 173 page  TMS570LS3137 SPNS162C – APRIL 2012 – REVISED APRIL 2015 www.ti.com 7 Peripheral Information and Electrical Specifications 7.1 Peripheral Legend Table 7-1. Peripheral Legend ABBREVIATION FULL NAME MibADC Analog To Digital Converter CCM-R4F CPU Compare Module - CortexR4F CRC Cyclic Redundancy Check DCAN Controller Area Network DCC Dual Clock Comparator DMA Direct Memory Access DMM Data Modification Module EMIF External Memory Interface ESM Error Signaling Module ETM-R4F Embedded Trace Macrocell - CortexR4F FTU FlexRay Transfer Unit GPIO General-Purpose Input/Output HTU High End Timer Transfer Unit I2C Inter-Integrated Circuit LIN Local Interconnect Network MIBSPI Multibuffer Serial Peripheral Interface N2HET Platform High-End Timer POM Parameter Overlay Module RTI Real-Time Interrupt Module RTP RAM Trace Port SCI Serial Communications Interface SPI Serial Peripheral Interface VIM Vectored Interrupt Manager 7.2 Multibuffered 12-Bit Analog-to-Digital Converter The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted. Table 7-2. MibADC Overview DESCRIPTION VALUE Resolution 12 bits Monotonic Assured Output conversion code 00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI] 116 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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