GS2985 datasheet(20/45 Pages) SEMTECH

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GS2985 Multi-Rate SDI Reclocker with Equalization &

De-emphasis

Data Sheet

36663 - 5

July 2012

20 of 45

Proprietary & Confidential

The default peak-gain setting upon power-up is optimized for compensating the

high-frequency losses associated with approximately 10 inches of 5-mil stripline in FR4

material.

The EQn_EN pins are multiplexed with the serial host interface pins. The EQn_EN functionality

is enabled when pin HIF is tied HIGH, as shown in Table 4-2:

4.4 4:1 Input Mux

The GS2985 incorporates a 4:1 input mux, which allows the connection of four independent

streams of video/data. There are four differential inputs (DDI[3:0] / DDI[3:0]). The active channel

can be selected via the DDI_SEL[1:0] pins as shown in Table 4-3.

The DDI_SEL pins include internal pull-downs, which pull the input voltage LOW if either pin

is unconnected. Active circuitry associated with the input buffers and trace EQ can only be

turned on for the selected input. Inputs which are not selected have their input buffers and trace

EQs turned OFF to save power. Unused inputs can be either left floating, or tied to VCC.

Table 4-1: Input Trace Equalization Operation

EQn_EN Setting

Trace Equalization Range

LOW

Low

HIGH

Medium

Table 4-2: EQn_EN Pins Multiplexed

Function

SDI/EQ0_EN

Active-high logic input to enable trace-equalization for high-speed input channel 0.

SDO/EQ1_EN

Active-high logic input to enable trace-equalization for high-speed input channel 1.

SCK/EQ2_EN

Active-high logic input to enable trace-equalization for high-speed input channel 2.

CS/EQ3_EN

Active-high logic input to enable trace-equalization for high-speed input channel 3.

Table 4-3: Input Selection Table

DDI_SEL[1:0]

Selected Input

DDI0

DDI1

DDI2

DDI3

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