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ADS1216 Datasheet(PDF) 7 Page - Texas Instruments

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Part # ADS1216
Description  8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER
PDF  28 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS1216 Datasheet(HTML) 7 Page - Texas Instruments

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7
ADS1216
SBAS171B
SPEC
DESCRIPTION
MIN
MAX
UNITS
t1
SCLK Period
4tOSC Periods
3
DRDY Periods
t2
SCLK Pulse Width, HIGH and LOW
200
ns
t3
CS LOW to first SCLK Edge; Setup Time(2)
0ns
t4
DIN Valid to SCLK Edge; Setup Time
50
ns
t5
Valid DIN to SCLK Edge; Hold Time
50
ns
t6
Delay between last SCLK edge for DIN and first SCLK
edge for DOUT:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM
50
tOSC Periods
CSREG, CSRAMX, CSRAM
200
tOSC Periods
CSARAM, CSARAMX
1100
tOSC Periods
t7(1)
SCLK Edge to Valid New DOUT
50
ns
t8(1)
SCLK Edge to DOUT, Hold Time
0
ns
t9
Last SCLK Edge to DOUT Tri-State
6
10
tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10
CS LOW time after final SCLK edge
0
ns
t11
Final SCLK edge of one op code until first edge SCLK
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
tOSC Periods
CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA,
RDATAC, STOPC
4
tOSC Periods
CREG, CRAM
220
tOSC Periods
CREGA
1600
tOSC Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
7
DRDY Periods
SELFCAL
14
DRDY Periods
RESET (Command, SCLK or Pin)
16
tOSC Periods
t12
300
500
tOSC Periods
t13
5tOSC Periods
t14
550
750
tOSC Periods
t15
1050
1250
tOSC Periods
t16
Pulse Width
4tOSC Periods
t17
DOR Data Not Valid
4
tOSC Periods
NOTE: (1) Load = 20pF
 10kΩ to DGND. (2) CS may be tied LOW.
TIMING DIAGRAMS
TIMING CHARACTERISTICS
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit Order = 0.
SCLK Reset Waveform
t
7
MSB(1)
LSB(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL = 1)
t
12
t
14
t
15
t
13
t
13
SCLK
t
17
DRDY
t
16
RESET, DSYNC, PDWN
ADS1216
Resets On
Falling Edge



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