ADS1216 datasheet(15/28 Pages) TI

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ADS1216

SBAS171B

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

00H

SETUP

SPEED

REF EN

REF HI

BUF EN

BIT ORDER

01H

MUX

PSEL3

PSEL2

PSEL1

PSEL0

NSEL3

NSEL2

NSEL1

NSEL0

02H

ACR

BOCS

IDAC2R1

IDAC2R0

IDAC1R1

IDAC1R0

PGA2

PGA1

PGA0

03H

IDAC1

IDAC1_7

IDAC1_6

IDAC1_5

IDAC1_4

IDAC1_3

IDAC1_2

IDAC1_1

IDAC1_0

04H

IDAC2

IDAC2_7

IDAC2_6

IDAC2_5

IDAC2_4

IDAC2_3

IDAC2_2

IDAC2_1

IDAC2_0

05H

ODAC

SIGN

OSET_6

OSET_5

OSET_4

OSET_3

OSET_2

OSET_1

OSET_0

06H

DIO

DIO_7

DIO_6

DIO_5

DIO_4

DIO_3

DIO_2

DIO_1

DIO_0

07H

DIR

DIR_7

DIR_6

DIR_5

DIR_4

DIR_3

DIR_2

DIR_1

DIR_0

08H

DEC0

DEC07

DEC06

DEC05

DEC04

DEC03

DEC02

DEC01

DEC00

09H

M/DEC1

DRDY

U/B

SMODE1

SMODE0

Reserved

DEC10

DEC09

DEC08

0AH

OCR0

OCR07

OCR06

OCR05

OCR04

OCR03

OCR02

OCR01

OCR00

0BH

OCR1

OCR15

OCR14

OCR13

OCR12

OCR11

OCR10

OCR09

OCR08

0CH

OCR2

OCR23

OCR22

OCR21

OCR20

OCR19

OCR18

OCR17

OCR16

0DH

FSR0

FSR07

FSR06

FSR05

FSR04

FSR03

FSR02

FSR01

FSR00

0EH

FSR1

FSR15

FSR14

FSR13

FSR12

FSR11

FSR10

FSR09

FSR08

0FH

FSR2

FSR23

FSR22

FSR21

FSR20

FSR19

FSR18

FSR17

FSR16

TABLE II. Registers.

ADS1216 REGISTER BANK TOPOLOGY

The operation of the device is set up through individual

registers. The set of the 16 registers required to configure the

device is referred to as a Register Bank, as shown in Figure 5.

Reads and Writes to Registers and RAM occur on a byte

basis. However, copies between registers and RAM occurs

on a bank basis. The RAM is independent of the Registers,

i.e.: the RAM can be used as general-purpose RAM.

The ADS1216 supports any combination of eight analog

inputs. With this flexibility, the device could easily support

eight unique configurations—one per input channel. In order

to facilitate this type of usage, eight separate register banks

are available. Therefore, each configuration could be written

once and recalled as needed without having to serially

retransmit all the configuration data. Checksum commands

are also included, which can be used to verify the integrity

of RAM.

The RAM provides eight “banks”, with a bank consisting of

16 bytes. The total size of the RAM is 128 bytes. Copies

between the registers and RAM are performed on a bank

basis. Also, the RAM can be directly read or written through

the serial interface on power-up. The banks allow separate

storage of settings for each input.

The RAM address space is linear, therefore accessing RAM

is done using an auto-incrementing pointer. Access to RAM

in the entire memory map can be done consecutively without

having to address each bank individually. For example, if

you were currently accessing bank 0 at offset 0xF (the last

location of bank 0), the next access would be bank 1 and

offset 0x0. Any access after bank 7 and offset 0xF will wrap

around to bank 0 and Offset 0x0.

Although the Register Bank memory is linear, the concept of

addressing the device can also be thought of in terms of bank

and offset addressing. Looking at linear and bank addressing

syntax, we have the following comparison: in the linear

FIGURE 5. Memory Organization.

memory map, the address 0x14 is equivalent to bank 1 and

offset 0x4. Simply stated, the most significant four bits

represent the bank, and the least significant four bits repre-

sent the offset. The offset is equivalent to the register

address for that bank of memory.

Configuration

Registers

16 bytes

SETUP

MUX

ACR

IDAC1

IDAC2

ODAC

DIO

DIR

DEC0

M/DEC1

OCR0

OCR1

OCR2

FSR0

FSR1

FSR2

RAM

128 Bytes

Bank 2

16 bytes

Bank 7

16 bytes

Bank 0

16 bytes

ADS1216 Datasheet(PDF) 15 Page - Texas Instruments

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