DS3134 datasheet(165/203 Pages) DALLAS

165 / 203 page

DS3134

165 of 203

Configuration Mode Figure 10.1C

PCI Bridge Mode

In the PCI Bridge Mode, data from the PCI bus can be transferred to the Local Bus. In this mode, the

Local Bus acts as a "master" and can create all the needed signals to control the bus. In the PCI Bridge

Mode, the user must configure the Local Bus Bridge Mode Control Register (LBBMC) which is described

in Section 10.2.

With 20 address lines, the Local Bus can address a 1M byte address space. The Host on the PCI bus will

determine where to map this 1M byte address space within the 32-bit address space of the PCI bus by

configuring the Base Address in the PCI Configuration Registers (see Section 9).

Bridge Mode 8 & 16 Bit Access

During a bus access by the Host, the Local Bus can determine how to map the four possible byte positions

from/to the PCI bus to/from the Local Bus data bus (LD) pins by examining the PCBE* signals and the

Local Bus Width (LBW) control bit which resides in the Local Bus Bridge Mode Control (LBBMC)

the PCBE* signals. The PCI data will be mapped to/from the LD[7:0] signal lines, the LD[15:0] signal

lines remain inactive. The Local Bus Block will drive the A0 and A1 address lines according to the

assertion of the PCBE* signals by the Host. See Table 10.1B for details. If the Host asserts more than

one of the PCBE* signals when the Local Bus is configured as an 8-bit bus, then the Local Bus will reject

the access and the PCI Block will return a Target Abort to the Host. See Section 9 for details on a Target

Abort.

T1 / E1

Framer or

Transceiver

Local Bus

DS3134 Chateau

Host

Processor

and Main

Memory

PCI /

Custom

Bus

lb_cnfgc

CPU Confgures and

Monitors DS3134

Local RAM &

ROM

Access

Allowed

Only Used to

Transfer HDLC

Data

T1 / E1

Framer or

Transceiver

T1 / E1

Framer or

Transceiver

T1 / E1

Framer or

Transceiver

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