DS3134 datasheet(167/203 Pages) DALLAS

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DS3134

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Bridge Mode Bus Arbitration

In the Bridge Mode, the Local Bus has the ability to arbitrate for bus access. In order for the feature to

operate, the Host must access the PCI Bridge Mode Control Register (LBBMC) and enable it via the

LARBE control bit (the default is bus arbitration disabled). If bus arbitration is enabled, then before a bus

transaction can occur, the Local Bus will first request bus access by asserting the LHOLD(LBR*) signal

and then wait for the bus to be granted from the Local Bus arbiter by sensing that the LHLDA(LBG*) has

been asserted. If the Host on the PCI Bus attempts a Local Bus access when the Local Bus is not granted

by the Local Bus master (LBGACK* is deasserted), then the Local Bus block will immediately inform the

Host that the Local Bus is busy and cannot be accessed at this time (in other words, come back later) by

issuing a PCI Target Retry. See Section 9 for details on the PCI Target Retry. When this happens, the

Local Bus block will not attempt the bus access and will keep the LA, LD, LBHE*, LWR*(LR/W*), and

LRD*(LDS*) signals tri-stated.

If the Host attempts a Local Bus access when the bus is busy, the Local Bus block will go ahead and

request bus access and after it has been granted, it will seize the bus for the time programmed into the

Local Bus Arbitration Timer (LAT0 to LAT3 in the LBBMC register) which can be from 32 to 1048576

clocks. As long as the local bus has been granted and the arbitration timer has at least 16 clocks left, then

the Host is allowed to access the Local Bus. See Figure 10.1D and the timing examples in Section 10.3

for more details.

Bridge Mode Bus Transaction Timing

When the Local Bus is operated in PCI Bridge Mode, the bus transaction time can be determined either

from an external ready signal (LRDY*) or from the PCI Bridge Mode Control Register (LBBMC) which

will allow a bus transaction time of 1 to 11 LCLK cycles. If the total access time to the Local Bus

exceeds 16 PCLK cycles, the PCI access will time out and a PCI Target Retry will be sent to the Host.

This will only occur when LRDY* has not been detected within 9 clocks. If this happens, the Local Bus

Error (LBE) status bit in the Status Master (SM) register will be set. Additional details on the LBE status

bit can be found in Section 4 and more details on transaction timing can be found in Figure 10.1D and the

timing examples in Section 10.3.

Bridge Mode Interrupt

In the PCI Bridge mode, the Local Bus can detect an external interrupt via the LINT* signal. If the Local

Bus detects that the LINTA* signal has been asserted, then it will set the LBINT status bit in the Status

Master (SM) register. The setting of this status bit can cause a hardware interrupt to occur at the PCI bus

via the PINTA* signal. This interrupt can be masked via the ISM register. See Section 4 for more

details.

Configuration Mode

In the Configuration Mode, the Local Bus is used only to configure the device and obtain status

information from the device. It is also used to configure the PCI Configuration Registers and hence the

PCI Bus signal PIDSEL is disabled when the Local Bus is in the Configuration Mode. Data cannot be

passed from the Local Bus to the PCI bus in this mode. The PCI bus will only be used as a high speed I/O

bus for the HDLC packet data. In this mode, bus arbitration, bus format, and the user settable bus

transaction time features are disabled. In the Configuration Mode, all bus accesses are based on 16-bit

addresses and 16-bit data. The upper four addresses (LA[19:16]) are ignored and 8-bit data accesses are

not allowed. See Section 12 for details on the AC timing requirements.

DS3134 Datasheet(PDF) 167 Page - Dallas Semiconductor

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