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DS3134 Datasheet(PDF) 178 Page - Dallas Semiconductor

Part # DS3134
Description  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3134 Datasheet(HTML) 178 Page - Dallas Semiconductor

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DS3134
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Figure 10.3H
8-Bit Write Cycle
Motorola Mode (LIM = 1)
Arbitration Disabled (LARBE = 0)
Bus Transaction Time = Timed from LRDY* (LRDY = 0000)
Note:
The LRDY* signal must be detected by the 9th LCLK or the bus access attempted by the Host will be
unsuccessful and the LBE status bit will be set.
lb_pm1_v2
10.3H\
03/22/99
LCLK
LA[19:0]
LD[7:0]
LD[15:8]
LR/W*
LDS*
Address Valid
LBHE*
LRDY*
tri-state
Data Valid
1234
56789
10



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