AD9121 datasheet(7/61 Pages) AD

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AD9121

Data Sheet

Rev. B | Page 6 of 60

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise

noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CMOS INPUTLOGIC LEVEL

Input VIN Logic High

IOVDD = 1.8 V

1.2

IOVDD = 2.5 V

1.6

IOVDD = 3.3 V

2.0

Input VIN Logic Low

IOVDD = 1.8 V

0.6

IOVDD = 2.5 V, 3.3 V

0.8

CMOS OUTPUT LOGIC LEVEL

Output VOUT Logic High

IOVDD = 1.8 V

1.4

IOVDD = 2.5 V

1.8

IOVDD = 3.3 V

2.4

Output VOUT Logic Low

IOVDD = 1.8 V, 2.5 V, 3.3 V

0.4

LVDS RECEIVER INPUTS1

Applies to data, DCI, and FRAME inputs

Input Voltage Range, VIA or VIB

825

1675

Input Differential Threshold, VIDTH

−100

+100

Input Differential Hysteresis, VIDTHH to VIDTHL

Receiver Differential Input Impedance, RIN

120

LVDS Input Rate

See Table 5

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage

Self-biasedinput, ac-coupled

1.25

Maximum Clock Rate

1230

MHz

REFCLK INPUT (REFCLKP, REFCLKN)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage

1.25

REFCLK Frequency (PLL Mode)

1 GHz ≤ fVCO ≤ 2.1 GHz

15.625

600

MHz

REFCLK Frequency (SYNC Mode)

See the Multichip Synchronization section

for conditions

600

MHz

SERIAL PORT INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High (tPWH)

12.5

Minimum Pulse Width Low (tPWL)

12.5

Setup Time, SDIO to SCLK (tDS)

1.9

Hold Time, SDIO to SCLK (tDH)

0.2

Data Valid, SDO to SCLK (tDV)

2.3

Setup Time, CS to SCLK (tDCSB)

1.4

1 LVDS receiver is compliant with the IEEE 1596reduced range link, unless otherwisenoted.

DIGITAL INPUT DATA TIMING SPECIFICATIONS

Table 3.

Parameter

Value

Unit

LATENCY (DACCLK CYCLES)

1× Interpolation(Withor Without Modulation)

Cycles

2× Interpolation(Withor Without Modulation)

135

Cycles

4× Interpolation(Withor Without Modulation)

292

Cycles

8× Interpolation(Withor Without Modulation)

608

Cycles

Inverse Sinc

Cycles

Fine Modulation

Cycles

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