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AD9121

Data Sheet

Rev. B | Page 18 of 60

THEORY OF OPERATION

The AD9121 combines manyfeatures that make it a very attractive

DAC for wired and wireless communications systems. The dual

digital signal path and dual DAC structure allowan easy interface

to common quadrature modulators when designing single side-

band (SSB) transmitters. The speed and performance of the

AD9121 allow wider bandwidths and more carriers to be syn-

thesized than in previously available DACs. In addition, the

AD9121 includes an innovative low power, 32-bit, complex

NCO that greatly increases the ease of frequency placement.

The AD9121 offers features that allow simplified synchroniza-

tion with incoming data and between multiple devices. Auxiliary

DACs are also provided on chip. The auxiliary DACs can be used

for output dc offset compensation (for LO compensation in SSB

transmitters) and for gain matching (for image rejection optimiza-

tion in SSB transmitters).

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing to many industry-standard micro-

controllers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including both the

Motorola SPI and Intel® SSR protocols. The interface allows

read/write access to all registers that configure the AD9121.

Single-byte or multiple-byte transfers are supported, as well as

MSB first or LSB first transfer formats. The serial port interface

can be configured as a single-pin I/O (SDIO) or as two unidi-

rectional pins for input and output (SDIO and SDO).

SCLK

SDIO

SDO

SPI

PORT

Figure 37. Serial Port Interface Pins

A communication cycle with the AD9121 has two phases.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first eight SCLK rising

edges. The instruction byte provides the serial port controller

with information regarding the data transfer cycle—Phase 2 of

the communication cycle. The Phase 1 instruction byte defines

whether the upcoming data transfer is a read or write, along with

the starting register address for the first byte of the data transfer.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the device.

A logic high on the CS pin followed by a logic low resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next eight rising SCLK edges represent the

instruction bits of the current I/O operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Registers change immediately

upon writing to the last bit of each transfer byte, except for the

frequency tuning word and NCO phase offsets, which change

only when the frequency tuning word (FTW) update bit

(Register 0x36, Bit 0) is set.

DATA FORMAT

The instruction byte contains the information shown in Table 9.

Table 9. Serial Port Instruction Byte

I7 (MSB)

I0 (LSB)

R/W

R/W, Bit 7 of the instruction byte, determines whether a read

or a write data transfer occurs after the instruction byte write.

Logic 1 indicates a read operation, and Logic 0 indicates a write

operation.

A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the

communication cycle. For multibyte transfers, A6 is the starting

byte address. The remaining register addresses are generated by

the device based on the LSB_FIRST bit (Register 0x00, Bit 6).

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 40 MHz. All datainput is registered on the rising edge

of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CS)

An active low input starts and gates a communication cycle.

It allows more than one device to be used on the same serial

communications lines. When the CS pin is high, the SDO and

SDIO pins go to a high impedance state. During the communica-

tion cycle, the CS pin should stay low.

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However, this

pin can be used as a bidirectional data line. The configuration

of this pin is controlled by Register 0x00, Bit 7. The default is

Logic 0, configuring the SDIO pin as unidirectional.

Serial Data Output (SDO)

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. If the device operates in a

single bidirectional I/O mode, this pin does not output data and

is set to a high impedance state.

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