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AD9121 Datasheet(PDF) 21 Page - Analog Devices |
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AD9121 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 61 page  AD9121 Data Sheet Rev. B | Page 20 of 60 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Addr (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x00 Comm SDIO LSB_FIRST Reset 0x00 0x01 Power control Power down I DAC Power down Q DAC Power downdata receiver Power down aux ADC 0x10 0x03 Data format Binary data format Q data first MSB swap Data Bus Width[1:0] 0x00 0x04 Interrupt enable Enable PLL lock lost Enable PLL locked Enable sync signal lost Enable sync signal locked Enable FIFO Warning 1 Enable FIFO Warning 2 0x00 0x05 Interrupt enable 0 0 0 Enable AED compare pass Enable AED compare fail Enable SED compare fail 0 0 0x00 0x06 Event flag PLL lock lost PLL locked Sync signal lost Sync signal locked FIFO Warning 1 FIFO Warning 2 N/A 0x07 Event flag AED compare pass AED compare fail SED compare fail N/A 0x08 Clock receiver control DACCLK duty correction REFCLK duty correction DACCLK cross- correction REFCLK cross- correction 1 1 1 1 0x3F 0x0A PLL control PLL enable PLL manual enable Manual VCO Band[5:0] 0x40 0x0C PLL control PLL Loop Bandwidth[1:0] PLL Charge Pump Current[4:0] 0xD1 0x0D PLL control N2[1:0] PLL cross- control enable N0[1:0] N1[1:0] 0xD9 0x0E PLL status PLL locked VCO Control Voltage[3:0] N/A 0x0F PLL status VCO Band Readback[5:0] N/A 0x10 Sync control Sync enable Data/FIFO rate toggle Rising edge sync Sync Averaging[2:0] 0x48 0x11 Sync control Sync Phase Request[5:0] 0x00 0x12 Sync status Sync lost Sync locked N/A 0x13 Sync status Sync Phase Readback[7:0] (6.2 format) N/A 0x15 Data receiver status LVDS FRAME level high LVDS FRAME level low LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low N/A 0x16 DCI delay DCI Delay[1:0] 0x00 0x17 FIFO control FIFO Phase Offset[2:0] 0x04 0x18 FIFO status FIFO Warning1 FIFO Warning 2 FIFO soft align ack FIFO soft align request N/A 0x19 FIFO status FIFO Level[7:0] N/A 0x1B Datapath control Bypass premod Bypass sinc−1 Bypass NCO NCO gain Bypass phase comp and dc offset Select sideband Send I data to Q data 0xE4 |
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