ST72754 datasheet(70/144 Pages) STMICROELECTRONICS

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SYNC PROCESSOR (SYNC) (Cont’d)

COUNTER CONTROL REGISTER (CCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = PSCD

Prescaler Enable bit.

0: Enable the Prescaler by 256

1: Disable the Prescaler and reset it to 7Fh. This

also disables the ICAP2 event.

Bit 6:5 = LCV1, LCV0

VSYNCO Extraction Control

Bit 4:0 = CV4-CV0

Counter Captured Value.

These bits contain the counter captured value in

different modes.

In VSYNCO extraction mode, they contain the

HSYNCI pulse-width measurement.

POLARITY REGISTER (POLR)

Bits 5-4 Read Only, other bits Read/Write

Reset Value: 0000 1000 (08h)

Bit 7 = SOG

Sync On Green Detector

SOG is set by hardware if CSYNCI pulse is not

included in the window between HSYNCI rising

edge and HSYNCI falling edge + dt .

Cleared by software.

Table 19. Sync On Green Window

Bit 6 = Reserved, forced by hardware to 0.

Bit 5 = VPOL

Vertical Sync polarity (read only)

0: Positive polarity

1: Negative polarity

Note: If the Vertical Sync polarity is changing, the VPOL

bit will be updated after a typical delay of 4 msec.

Bit 4 = 2FHDET

Detection of Pre/Post Equalization

pulses (read only).

This bit is continuously updated by hardware. It is

valid when the sync generator and horizontal

analyzer are disabled (HVGEN = 0, HACQ = 0).

0: None detected

1: Pre/Post Equalization pulses detected

Bit 3 = HVSEL

Alternate Sync Input Select.

This bit selects between the two sets of Horizontal

and Vertical Sync inputs

0: HSYNCI2 / VSYNCI2

1: HSYNCI1 / VSYNCI1

Bit 2 = VCORDIS

Extension Disable Signal

(Extension with VGENR Register)

0: enable

1: disable

Bit 1 = CLPINV

Programmable ClampOut pulse

polarity.

0: Positive

1: Negative

Bit 0 = BLKINV

Programmable blanking polarity

0: Negative

1: Positive

PSCD

LCV1

LCV0 CV4 CV3 CV2 CV1

CV0

LCV1

LCV0

VSYNC0 Control Bits

Normal mode

Counter capture on input falling edge

Normal mode

Counter capture on input rising edge

Extraction mode

CSYNCI/HSYNCI Negative polarity

CV4-0 = counter minimum threshold

Extraction mode

CSYNCI/HSYNCI Positive polarity

CV4-0 = counter maximum threshold

SOG

VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV

WINDOW DELAY

min.

max.

165 ns

250 ns

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