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16-BIT TIMER (Cont’d)

4.3.3.4 Output Compare

In this section, the index,

i, may be 1 or 2.

This function can be used to control an output

waveform or indicating when a period of time has

elapsed.

When a match is found between the Output

Compare register and the free running counter, the

output compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the free

running counter each timer clock cycle.

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

Timing resolution is one count of the free running

counter: (

fCPU/(CC1.CC0)).

Procedure

To use the output compare function, select the

following in the CR2 register:

– Set the OC

iE bit if an output is needed then the

OCMP

i pin is dedicated to the output compare i

function.

– Select the timer clock (CC1-CC0) (see Table 15

Clock Control Bits).

And select the following in the CR1 register:

– Select the OLVL

i bit to applied to the OCMPi pins

after the match occurs.

– Set the OCIE bit to generate an interrupt if it is

needed.

When match is found:

– OCF

i bit is set.

– The OCMP

i pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset and stays low

until valid compares change it to a high level).

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

Clearing the output compare interrupt request is

done by:

3. Reading the SR register while the OCF

i bit is

set.

4. An access (read or write) to the OC

iLR register.

Note: After a processor write cycle to the OC

iHR register,

the output compare function is inhibited until the

iLR register is also written.

If the OC

iE bit is not set, the OCMPi pin is a

general I/O port and the OLVL

i bit will not appear

when match is found but an interrupt could be

generated if the OCIE bit is set.

The value in the 16-bit OCiR register and the OLV

bit should be changed after each successful

comparison in order to control an output waveform

or establish a new elapsed timeout.

The OCiR register value required for a specific

timing application can be calculated using the

following formula:

Where:

∆t

= Desired output compare period (in

seconds)

fCPU

= Internal clock frequency

CC1-CC0 = Timer clock prescaler

The following procedure is recommended to

prevent the OCF

i bit from being set between the

time it is read and the write to the OCiR register:

– Write to the OC

iHR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

i bit, which may be already set).

– Write to the OC

iLR register (enables the output

compare function and clears the OCF

i bit).

MS Byte

LS Byte

iROCiHR

iLR

∆ OCiR = ∆

t * fCPU

(CC1.CC0)

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