ST72754 datasheet(61/144 Pages) STMICROELECTRONICS

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SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6 Input Processing

4.4.6.1 Detecting Signal Presence

The Sync Processor provides two ways of

checking input signal presence, by directly polling

the LATR Latch Register or using the Timer

interrupts.

Polling check

Use the Latch Register (LATR), to detect the

presence

HSYNCI,

VSYNCI,

CSYNCI,

HFBACK and VFBACK signals. These latched bits

are set when the falling edge of the corresponding

signal is detected. They are cleared by software.

Interrupts check

Due to the fact that VSYNCI is connected to Timer

Input Capture 1 and HSYNCI or CSYNCI is

connected to Timer Input Capture 2, the Timer

interrupts can be used to detect the presence of

input signals. Refer to the 16-bit Timer chapter for

the description of the Timer registers.

To use the interrupt method:

– Select Input Capture1 edge detection:

IEDG1 bit in the Timer CR1 register

– Select Input Capture 2 edge detection (must be

falling edge):

IEDG2 bit = 0 in the Timer CR2 register

– Enable Timer Input Capture interrupts:

ICIE bit in the Timer CR1 register.

– Select the Hsync and Vsync input signals:

HVSEL bit in the POLR register

– Enable the prescaler for HSYNCI or CSYNCI

signal:

PSCD bit in the CCR register.

– Select the normal mode:

LCV1/LCV0 bits in the CCR register.

Perform any of the following:

– Check for VSYNCI presence by monitoring inter-

rupt requests from Timer ICAP1. When VSYNCI

is detected then either detect the VSYNCI polar-

ity or check for HSYNCI presence.

– Check for HSYNCI presence by monitoring inter-

rupt requests from Timer ICAP2. On detecting

HSYNCI, either detect its polarity or check if the-

composite sync on HSYNCI pin is detected or

check for CSYNCI presence.

– Check for CSYNCI presence by monitoring inter-

rupt requests from Timer ICAP2.

4.4.6.2 Measuring Sync Period

To measure the sync period, the Sync processor

block uses the Timer Input Capture interrupts:

– ICAP1 connected to VSYNCI signal

– ICAP2 connected to HSYNCI/CSYNCI signal

with a 256 prescaler

Calculating

the

difference

between

two

subsequent Input Captures (16-bit value) gives the

period for 256xPH (horizontal period) and PV

(vertical period).

The period accuracy is one timer clock (500ns at 2

MHz), so that the tolerance is 500ns for PH and

256 * PH (PH accuracy =1.95ns).

Notes:

1) In case of composite sync, the HSYNCI period

measurement can be synchronized on the

VSYNCI pulse by setting and resetting the

prescaler PSCD bit in the CCR register (for this

function, the ICAP2 detection must be selected

as falling edge).

This avoids errors in the period measurement

due to the Vsync pulse.

2) The Timer Interrupt request should be masked

during a write access to any of the Sync

processor control registers.

Important Note:

Since the recognition of the video mode relies

on the accuracy of the measurements, it is

highly recommended to implement a counter-

style

algorithm

which

performs

several

consecutive measurements before switching

between modes.

The purpose of this algorithm is to filter out any

glitches occurring on the video signals.

ST72754 Datasheet(PDF) 61 Page - STMicroelectronics

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