ST72754 datasheet(50/144 Pages) STMICROELECTRONICS

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16-BIT TIMER (Cont’d)

4.3.3.7 Pulse Width Modulation Mode

Pulse

Width

Modulation

mode

enables

the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

The pulse width modulation mode uses the

complete Output Compare 1 function plus the

OC2R register.

Procedure

To use pulse width modulation mode select the

following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OC2R register.

And select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated

to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC1-CC0) (see Table 15

Clock Control Bits).

Load

the

OC2R

with

the

value

corresponding to the period of the signal.

Load

the

OC1R

with

the

value

corresponding to the length of the pulse if

(OLVL1=0 and OLVL2=1).

If OLVL1=1 and OLVL2=0 the length of the pulse is

the difference between the OC2R and OC1R

registers.

The OCiR register value required for a specific

timing application can be calculated using the

following formula:

Where:

– t = Desired output compare period (seconds)

–fCPU = Internal clock frequency (see Miscella-

neous register)

– CC1-CC0 = Timer clock prescaler

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 36).

Note: After a write instruction to the OC

iHR register, the

output compare function is inhibited until the OC

iLR

The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited. The Input Capture

interrupts are available.

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Figure 36. Pulse Width Modulation Mode Timing

iR Value =

t * fCPU

(CC1.CC0)

- 5

Counter

Counter is reset

to FFFCh

OCMP1 = OLVL2

Counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

COUNTER

34E2

FFFC FFFD FFFE

2ED0 2ED1 2ED2

34E2

FFFC

OLVL2

OLVL1

OCMP1

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

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