ST72754 datasheet(39/144 Pages) STMICROELECTRONICS

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4.2 WATCHDOG TIMER (WDG)

4.2.1 Introduction

The Watchdog timer is used to detect the

occurrence of a software fault, usually generated

by external interference or by unforeseen logical

conditions, which causes the application program

to abandon its normal sequence. The Watchdog

circuit generates an MCU reset on expiry of a

programmed time period, unless the program

refreshes the counter’s contents before the T6 bit

becomes cleared.

4.2.2 Main Features

Programmable timer (64 increments of 49152

CPU cycles)

Programmable reset

Reset (if watchdog activated) when the T6 bit

reaches zero

Figure 26. Watchdog Block Diagram

4.2.3 Functional Description

The counter value stored in the CR register (bits

T6:T0), is decremented every 49,152 machine

cycles, and the length of the timeout period can be

programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates a

reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the CR

regular

intervals

during

normal

operation to prevent an MCU reset. The value to

be stored in the CR register must be between FFh

and C0h (see Table 13 . Watchdog Timing (fCPU =

8 MHz)):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

RESET

WDGA

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷49152

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