ST72754 datasheet(100/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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DDC INTERFACE (Cont’d)

The Write and Read operations allow the EDID

data to be downloaded during factory alignment

(for example).

Writes to the memory by the DMA engine can be

inhibited by means of the WP bit in the DCR

A write of the last data structure byte sets a flag

and may be programmed to generate an interrupt

request.

The Data address (sub-address) is either the

second byte of write transfers or is pointed to by

the

internal

address

counter

automatically

incremented after each byte transfer.

Physical address mapping of the data structure

within the memory space is performed with a

dedicated register accessible by software.

4.8.5.1.2 Mode description

DDC1 Mode: This mode is only enabled when the

DDC v2 or P&D-DDC v2 standards are validated. It

transmits only the EDID v1 data (128 bytes).

To switch the DDC1/2B Interface to DDC1 mode,

software must first clear the CF0 bit in the DCR

HWPE bit to enable the DDC1/2B Interface.

A proper initialization sequence (see Figure 59)

must supply nine clock pulses on the VSYNCI pin

in order to internally synchronize the device.

During this initialization sequence, the SDA pin is

in high impedance. On the rising edge of the 10th

pulse applied on VSYNCI, the device outputs on

SDA the most significant (MSB) bit of the byte

located at data address 00h.

A byte is clocked out by means of 9 clock pulses

on Vsync, 8 clock pulses for the data byte itself and

an extra pulse for a Don’t Care bit.

As long as SCL is not held low, each byte of the

memory array is transmitted serially on SDA.

The internal address counter is incremented

automatically until the last byte is transmitted.

Then, it rolls over to relative location 00h.

The physical mapping of the data structure

depends on the configuration and on the content of

the AHR register which can be set by software

(see Figure 60).

Figure 59. DDC1 Waveforms

Vsync

SDA

Bit 7

SCL

Bit 6

ALR

00h

Vsync

SDA

Bit 7

SCL

Bit 6

ALR

00h

7Fh

Bit 7

Bit 6

Bit 0

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