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ST72754 Datasheet(PDF) 88 Page - STMicroelectronics |
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ST72754 Datasheet(HTML) 88 Page - STMicroelectronics |
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88 / 144 page ![]() ST72774/ST727754/ST72734 88/144 I²C SINGLE MASTER BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. The speed of the I2C interface may be selected between Standard (0-100KHz) and Fast I2C (100- 400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating open-drain output or floating input. In this case, the value of the external pull-up resistance used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 53. I2C Interface Block Diagram DATA REGISTER (DR) DATA SHIFT REGISTER CLOCK CONTROL REGISTER (CCR) STATUS REGISTER 1 (SR1) CONTROL REGISTER (CR) SDAI SCLI CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT CLOCK CONTROL DATA CONTROL SCL SDA |
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