16F630 datasheet(32/132 Pages) MICROCHIP

32 / 132 page

PIC16F630/676

DS40039C-page 30

 2003 Microchip Technology Inc.

4.3

Using Timer0 with an External

Clock

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI, with the internal phase clocks, is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T0CKI to be high for at least 2T

OSC (and

a small RC delay of 20 ns) and low for at least 2T

OSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

OPTION_REG — OPTION REGISTER (ADDRESS: 81h)

Note:

The ANSEL (9Fh) and CMCON (19h)

registers must be initialized to configure an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC16F676.

R/W-1

RAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

bit 7

bit 0

bit 7

RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled

0 = PORTA pull-ups are enabled by individual port latch values

bit 6

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin

0 = Interrupt on falling edge of RA2/INT pin

bit 5

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA2/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin

0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0

PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value

TMR0 Rate WDT Rate

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