16F630 datasheet(67/132 Pages) MICROCHIP

67 / 132 page

 2003 Microchip Technology Inc.

DS40039C-page 65

PIC16F630/676

9.4.1

RA2/INT INTERRUPT

External interrupt on RA2/INT pin is edge-triggered;

either rising if INTEDG bit (OPTION<6>) is set, or

falling, if INTEDG bit is clear. When a valid edge

appears

the

RA2/INT

pin,

the

INTF

bit

(INTCON<1>) is set. This interrupt can be disabled by

clearing the INTE control bit (INTCON<4>). The INTF

bit must be cleared in software in the Interrupt Service

Routine before re-enabling this interrupt. The RA2/INT

interrupt can wake-up the processor from SLEEP if the

INTE bit was set prior to going into SLEEP. The status

of the GIE bit decides whether or not the processor

branches to the interrupt vector following wake-up. See

Section 9.7 for details on SLEEP and Figure 9-13 for

timing of wake-up from SLEEP through RA2/INT

interrupt.

9.4.2

TMR0 INTERRUPT

An overflow (FFh

→ 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

enabled/disabled

setting/clearing

T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 4.0.

9.4.3

PORTA INTERRUPT

An input change on PORTA change sets the RAIF

(INTCON<0>) bit. The interrupt can be enabled/

disabled by setting/clearing the RAIE (INTCON<3>)

bit. Plus individual pins can be configured through the

IOCA register.

9.4.4

COMPARATOR INTERRUPT

See Section 6.9 for description of comparator interrupt.

9.4.5

A/D CONVERTER INTERRUPT

After a conversion is complete, the ADIF flag (PIR<6>)

is set. The interrupt can be enabled/disabled by setting

or clearing ADIE (PIE<6>).

See Section 7.0 for operation of the A/D converter

interrupt.

FIGURE 9-11:

INT PIN INTERRUPT TIMING

Note:

The ANSEL 9Fh) and CMCON (19h)

registers must be initialized to configure an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC16F676.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF inter-

rupt flag may not get set.

OSC1

CLKOUT

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

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