| Electronic Components Datasheet Search |
|
PM5347 Datasheet(PDF) 277 Page - PMC-Sierra, Inc |
|
|
|||||||||||||||||||||||||||||
PM5347 Datasheet(HTML) 277 Page - PMC-Sierra, Inc |
|
277 / 302 page ![]() PM5347 S/UNI-PLUS DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 261 17 S/UNI-PLUS TIMING CHARACTERISTICS (TC = -40°C to +85°C, VDD = 5 V ±5%) Table 16 - Line Side Receive Interface (Figure 37) Symbol Description Min Max Units RRCLK+/RRCLK- Duty Cycle 51.84 or 155.52 MHz (RBYP high) 45 55 % 19.44 or 6.48 MHz (RBYP low) 30 70 RXD+/RXD- Operating Frequency STS-3c/STM-1 (RBYP high) 156 Mbit/s STS-3c/STM-1 (RBYP low) 155 156 Mbit/s STS-1 (RBYP high) 52 Mbit/s STS-1 (RBYP low) 51 52 Mbit/s RRCLK+/RRCLK- Frequency Tolerance† -20 +20 ppm tSRXD RXD+/RXD- Setup time to RRCLK+/RRCLK- (RBYP asserted high.) 1ns tHRXD RXD+/RXD- Hold time to RRCLK+/RRCLK- (RBYP asserted high.) 1.5 ns † Note: The specification may be relaxed to +/- 50 ppm if the S/UNI-PLUS is not loop timed, or for applications that do not require this timing accuracy. If loop timing is enabled, the tighter tolerance is required to meet the SONET free run accuracy specification under loss of signal conditions. Frequency tolerance is measured with respect to the receive stream on RXD+/- when clock recovery is enabled (RBYP is low). |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |